Exploiting program execution phases to trade power and performance for media workload

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2004, Pages 387-389

  Banerjee, Subhasis ^a   Surendra, G ^a   Nandy, S K ^a  

^a INDIAN INSTITUTE OF SCIENCE   (India)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BENCHMARKING; COMPUTER PROGRAMMING; COMPUTER SIMULATION; DECODING; MICROPROCESSOR CHIPS; PARALLEL PROCESSING SYSTEMS; PIPELINE PROCESSING SYSTEMS;

ENERGY DELAY PRODUCTS (EDP); PROGRAM EXECUTION; STREAMING MEDIA; SUPERSCALAR PROCESSORS;

MULTIMEDIA SYSTEMS;

EID: 2442597054     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

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2. R. Gonzalez, and M. Horowitz, "Energy Dissipation in General Purpose Microprocessors," In IEEE Journal of Solid State Circuits, 31(9), pp. 1277-1284, 1996.
3. D. Folegnani and A. Gonzalez, "Energy-Effective Issue Logic," In Proc. of the Int. Symp. on Computer Architecture, 2001.
4. D. Burger, T.M Austin, and S. Bennet, "Evaluating Future Microprocessors: The SimpleScalar Tool Set," Technical Report CS-TR-96-1308, University of Wisconsin-Madison, July 1996.
5. th Intn'l. Symp. on Computer Architecture, June 2000.
6. M. Guthaus, J. Ringenberg, D. Ernst, T. Austin, T. Mudge, R. Brown, "MiBench: A free, commercially representative embedded benchmark suite," In IEEE 4th Annual Workshop on Workload Characterization, Dec 2001.