The hierarchical timing pair model for multirate DSP applications

IEEE Transactions on Signal Processing

Volumn 52, Issue 5, 2004, Pages 1209-1217

  Chandrachoodan, Nitin ^a   Bhattacharyya, Shuvra S ^a   Liu, K J Ray ^a  

^a UNIVERSITY OF MARYLAND   (United States)

Author keywords

Hierarchical dataflow graphs; High level design; Iteration period; Multirate DSP; Timing analysis

Indexed keywords

ADDERS; ALGORITHMS; COMPUTER SIMULATION; GRAPH THEORY; SEQUENTIAL CIRCUITS;

HIERARCHICAL DATAFLOW GRAPHS; HIERARCHICAL TIMING PAIR MODEL; HIGH-LEVEL DESIGN; MULTIRATE DIGITAL SIGNAL PROCESSING; TIMING ANALYSIS;

DIGITAL SIGNAL PROCESSING;

EID: 2442541253     PISSN: 1053587X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSP.2004.826178     Document Type: Article

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