Efficient reachability checking using sequential SAT

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2004, Pages 418-423

  Parthasarathy, G ^a   Iyer, M K ^a   Cheng, K T ^a   Wang, Li C ^a  

^a University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BREADTH FIRST SEARCH (BFS); DEPTH FIRST SEARCH (DFS); IMAGE COMPUTATION; SEQUENTIAL SEARCH TECHNIQUES;

BOOLEAN ALGEBRA; COMPUTATIONAL METHODS; COMPUTER SCIENCE; DIGITAL IMAGE STORAGE; OPTIMIZATION; SEQUENTIAL CIRCUITS; STATE SPACE METHODS;

LEARNING SYSTEMS;

EID: 2442540208     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)

1. A. NARAYAN, J. JAIN, R. K. BRAYTON, AND A. L. SANGIOVANNI-VINCENTELLI. Reachability analysis using partitioned ROBDDs. In Proc. of the IEEE/ACM ICCAD (November 1993), pp. 388-393.
2. BIERE, A., AND KUNZ, W. SAT and ATPG: Boolean Engines for Formal Hardware Verification. In Proc. of the IEEE/ACM ICCAD (November 2002).
3. CLARKE, E., GRUMBERG, O., AND PELED, D. Model Checking. MIT Press, 1999.
4. FUJIWARA, H. FAN: a Fanout-oriented Test Pattern Generation Algorithm. In Proc. of ISCAS (June 1985), pp. 671-674.
5. GUPTA, A., YANG, Z., ASHAR, P., ZHANG, L., AND MALIK, S. Partition-Based Decision Heuristics for Image Computation using SAT and BDDs. In Proc. of the IEEE/ACM ICCAD (November 2001), pp. 286-292.
6. J.GIRALDI, AND M.L. BUSHNELL. Search State Equivalence for Redundancy Identification and Test Generation. In Proc. of ITC (Oct. 1991), pp. 184-193.
7. K.-T. CHENG, AND A. KRSTIC. Current Directions in Automatic Test-Pattern Generation. IEEE Computer 32, 11 (1999), 58-64.
8. H.-J. KANG AND I.-C. PARK. SAT-based Unbounded Symbolic Model Checking. In 40th ACM/IEEE DAC (2003).pp. 840-843.
9. M. MOSKIEWICZ, C. MADIGAN, Y. ZHAO, L. ZHANG, AND S. MALIK. Engineering an Efficient SAT Solver. In 38th ACM/IEEE DAC (2001).
10. MARCHOK, T., EL-MALEH, A., MALY, W., AND RAJSKI, J. A Complexity Analysis of Sequential ATPG. IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems. 15 n 11 (Nov. 1996), 1409-1423.
11. th CAV (2002), vol. 2402 of LNCS, Springer-Verlag, pp. 250-264.
12. M.K. IYER, G. PARTHASARATHY, AND K.-T. CHENG. SATORI - A Fast Sequential SAT Solver for Circuits, In Proceedings of the ICCAD, (November 2003). pp. 320-325.
13. R. K. BRAYTON, AND G. D. HACHTEL et. al. VIS: A System for Verification and Synthesis. In Proc. of CAV (July/August 1996), vol. 1102 of LNCS, Springer Verlag, pp. 428-432.
14. RUDELL, R., AND SANGIOVANNI-VINCENTELLI, A. Exact Minimization of Multiple-valued Functions for PLA optimization. In Proc. of the IEEE/ACM ICCAD (Nov. 1986), pp. 354-360.
15. S. SHENG, AND M. HSIAO. Efficient Preimage Computation using a Novel Success-Driven ATPG. In Proc. of DATE'2003 (March 2003), pp. 822-827.
16. WILLIAMS, P. F., BIERE, A., CLARKE, E. M., AND GUPTA, A. Combining Decision Diagrams and SAT Procedures for Efficient Symbolic Model Checking. In Proc of CAV (2000), pp. 124-138.
17. ZHANG, L., MADIGAN, C., MOSKEWICZ, M., AND MALIK, S. Efficient Conflict Driven Learning in a Boolean Satisfiability Solver. In Proc. of the IEEE/ACM ICCAD (November 2002).