Non-linearly separable cluster classification: An application for a pulse-coded CMOS neuron

Intelligent Engineering Systems Through Artificial Neural Networks

Volumn 13, Issue , 2003, Pages 63-67

  Konduri, Sai Ramesh J Rao ^a   Frenzel, James F ^a  

^a UNIVERSITY OF IDAHO   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; MOSFET DEVICES; NEURAL NETWORKS; NEUROLOGY; OSCILLATORS (ELECTRONIC); PERSONNEL TRAINING; SPURIOUS SIGNAL NOISE; VLSI CIRCUITS;

NEURONS; PARALLEL SYSTEMS; THRESHOLD CIRCUITS; WINNER-TAKE-ALL (WTA) NETWORKS;

CMOS INTEGRATED CIRCUITS;

EID: 2442519101     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

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8. Polikar, R., Udpa, L., and Udpa, S. S., 1999, "Nonlinear Cluster Transformations for Increasing Pattern Separablity," Proceedings, IJCNN International Joint Conference on Neural Networks, Vol. 6, pp. 4006-4011.
9. Su, M.-C., DeClaris, N., and Liu, T.-K., 1997, "Application of Neural Networks in Cluster Analysis," IEEE international conference on Systems, Man and Cybernetics, Vol. 1, pp. 1-6.
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