3-D capacitance extraction of IC interconnects using field solvers and homogenization technique

IEEE Transactions on Magnetics

Volumn 40, Issue 2 II, 2004, Pages 703-706

  Ren, Z ^a   Lage, C ^a  

^a CADENCE DESIGN SYSTEMS   (United States)

Author keywords

Homogenization of multilayered media; VLSI circuit parameter extraction

Indexed keywords

BOUNDARY ELEMENT METHOD; CAPACITANCE; COMPUTATIONAL METHODS; COMPUTER SIMULATION; DIELECTRIC MATERIALS; ELECTROMAGNETIC FIELDS; FINITE ELEMENT METHOD; MAGNETIC ANISOTROPY; MATHEMATICAL MODELS; VLSI CIRCUITS;

CAPACITANCE EXTRACTION; FIELD SOLVERS; HOMOGENIZATION; MESHING;

INTEGRATED CIRCUITS;

EID: 2342630719     PISSN: 00189464     EISSN: None     Source Type: Journal    
DOI: 10.1109/TMAG.2004.825422     Document Type: Article

References (4)

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3. M. Bachtold, M. Spasojevic, C. Lage, and P. B. Ljung, ''A system for full-chip and critical net parasitic extraction for ULSI interconnects using a fast 3D field solver," IEEE Trans. Computer-Aided Design, vol. 19, pp. 325-338, Mar. 2000.
4. Y. L. Le Coz and R. B. Iverspn, "Stochastic algorithm for high speed capacitance extraction in integrated circuits," Solid-State Electron., vol. 35, no. 7, pp. 1005-101, 1992.