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Volumn 2147, Issue , 2001, Pages 17-26

An emulator for exploring RaPiD configurable computing architectures

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; COMPUTATION THEORY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); IMAGE PROCESSING; MEMORY ARCHITECTURE;

EID: 23044529139     PISSN: 03029743     EISSN: 16113349     Source Type: Journal    
DOI: 10.1007/3-540-44687-7_3     Document Type: Article
Times cited : (15)

References (8)
  • 4
    • 0022482205 scopus 로고
    • Partitioning and mapping algorithms into fixed size systolic arrays
    • Moldovan, D. I. and Fortes, J. A. B.,.Partitioning and mapping algorithms into fixed size systolic arrays., IEEE Transactions on Computers, 1986, pp.1-12.
    • (1986) IEEE Transactions on Computers , pp. 1-12
    • Moldovan, D.I.1    Fortes, J.2
  • 5
    • 0024143306 scopus 로고
    • Synthesizing linear array algorithms from nested FOR loop algorithms
    • Lee, P. and Kedem, Z. M.,.Synthesizing linear array algorithms from nested FOR loop algorithms., IEEE Transactions on Computers, 1988, pp.1578-98.
    • (1988) IEEE Transactions on Computers , pp. 1578-1598
    • Lee, P.1    Kedem, Z.M.2
  • 7
    • 85018990900 scopus 로고    scopus 로고
    • Xilinx. "Virtex and Virtex-E Overview, 16 Mar
    • Xilinx. "Virtex and Virtex-E Overview." http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=ss_vir (16 Mar. 2001).
    • (2001)
  • 8
    • 85018956832 scopus 로고    scopus 로고
    • Intel. "StrongARM SA-110 Multimedia Development Board with Companion SA-1101 Developement Board". Order Number: 278253-001 Jan. 1999, 16 Mar
    • Intel. "StrongARM SA-110 Multimedia Development Board with Companion SA-1101 Developement Board". Order Number: 278253-001 Jan. 1999. ftp://download.intel.com/design/strong/datashts/27825301.pdf (16 Mar. 2001).
    • (2001)


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.