New reliability failure mechanism in porous low-k dual damascene interconnects

Advanced Metallization Conference (AMC)

Volumn , Issue , 2003, Pages 277-281

  Augur, R A ^a,b,i   Kim, C U ^c   Blaschke, V ^a,d,j   Michael, N L ^c   Gillespie, P ^a,e   Rasco, M ^a,f   Lin, J C ^a,g   Kim, S Y ^a,h   Pfeifer, K ^a,b  

^a SEMATECH   (United States)

^b NXP SEMICONDUCTORS   (Netherlands)

^c UNIVERSITY OF TEXAS AT ARLINGTON   (United States)

^d Conexant Systems Inc ^*  (United States)

^e TEXAS INSTRUMENTS   (United States)

^f MOTOROLA INC   (United States)

^g TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

^h Hynix Semiconductor Inc   (South Korea)

ⁱ IBM   (United States)

^j Jazz Semiconductor   (United States)

more..

Author keywords

[No Author keywords available]

Indexed keywords

LOW-K DIELECTRICS; LOW-K DUAL DAMASCENE INTERCONNECTS; METAL BARRIER INTEGRITY; RELIABILITY TESTING;

CHEMICAL MECHANICAL POLISHING; CHEMICAL VAPOR DEPOSITION; COPPER; OXIDATION; PHYSICAL VAPOR DEPOSITION; RELIABILITY;

OPTICAL INTERCONNECTS;

EID: 22944459009     PISSN: 15401766     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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