Design of a power-reduction Viterbi decoder for WLAN applications

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 52, Issue 6, 2005, Pages 1148-1156

  Lin, Chien Ching ^a   Shih, Yen Hsu ^a   Chang, Hsie Chia ^a   Lee, Chen Yi ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Add compare select; Path merging; Path prediction; Survivor memory; Viterbi decoder

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DATA STORAGE EQUIPMENT; LOCAL AREA NETWORKS; PROBABILITY; WIRELESS TELECOMMUNICATION SYSTEMS;

ADD-COMPARE-SELECT; PATH MERGING; PATH PREDICTION; SURVIVOR MEMORY; VITERBI DECODER; WIRELESS LOCAL AREA NETWORKS (WLAN);

DECODING;

EID: 22144471245     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2005.849106     Document Type: Article

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