A new architecture for the fast viterbi algorithm

IEEE Transactions on Communications

Volumn 51, Issue 10, 2003, Pages 1624-1628

  Lee, Inkyu ^a   Sonntag, Jeff L ^b  

^a Korea University   (South Korea)

^b Accelerant Networks   (United States)

Author keywords

Detector decoder; Fast architecture; Viterbi algorithm (VA)

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; CONVOLUTIONAL CODES; ERROR CORRECTION; MAXIMUM LIKELIHOOD ESTIMATION; TRELLIS CODES;

ADD-COMPARE-SELECT UNIT; BLOCK-PROCESSING APPROACH; MAXIMUM LIKELIHOOD SEQUENCE ESTIMATION; VITERBI ALGORITHM;

DECODING;

EID: 0242365691     PISSN: 00906778     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCOMM.2003.818100     Document Type: Letter

References (11)

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