High density and low power design of MRAM

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2004, Pages 575-578

  Hung, C C ^a   Kao, M J ^a   Chen, Y S ^a   Wang, Y H ^a   Hsu, H H ^a   Chen, C M ^a   Lee, Y J ^a   Chen, W C ^a   Lee, J Y ^a   Chen, W S ^a   Lin, W C ^b   Shen, K H ^a   Wei, J H ^a   Wang, L C ^a   Chen, K L ^a   Chao, S ^c   Tang, D D ^b   Tsai, M J ^a  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

^b TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

^c NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; ELECTRIC BATTERIES; MAGNETORESISTANCE; PACKING; SCHEMATIC DIAGRAMS; SPEED; TRANSISTORS; ELECTRIC POWER SUPPLIES TO APPARATUS; MAGNETIC STORAGE;

HIGH PACKING DENSITY; LOW POWER DESIGN; MAGNETORESISTIVE RANDOM ACESS MEMORY (MRAM); PILLAR WRITE WORD LINE (PWWL);

RANDOM ACCESS STORAGE; MAGNETIC RECORDING;

BIT SIZE; DENSITY POWER; HIGH SPEED; LOW-POWER DESIGN; MEMORY APPLICATIONS; NONVOLATILITY; STRUCTURE-BASED; UNIVERSAL MEMORY; WRITING CURRENTS;

EID: 21644474934     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. T. Tsuji, H. Tanizaki, M. Ishikawa, J. Otani, Y. Yamaguchi, S. Ueno, et al., "A 1.2V 1Mbit embedded MRAM core with folded bit-line array architecture", Symposium on VLSI Circuits, p. 450, 2004.
2. J. DeBrosse, C. Arndt, C. Barwin, A. Bette, D. Gogl, E. Gow, et al., "A 16 Mb MRAM featuring bootstrapped write drivers", Symposium on VLSI Circuits, p. 454, 2004.
3. N. Sakimura, T. Sugibayashi, T. Honda, S. Miura, H. Numata, H. Hada, et al., "A 512kb cross-point cell MRAM", IEEE ISSCC Tech. Dig., p. 278, 2003.
4. D. Gogl and T. Schlösser, "MRAM configuration", US Patent 6,421,271 B1, 2002.
5. C.C. Hung, M.J. Kao, W.C. Lin, S. Chao, D.D. Tang and M.-J. Tsai, "Low writing current magnetoresistive random access memory (MRAM) with side metal pillar write word line (PWWL)", J. Magn. Magn. Mater., in press.
6. M. Durlam, P.J. Naji, A. Omair, M. DeHerrera, J. Calder, J.M. Slaughter, et al., "A 1-Mbit MRAM based on 1T1MTJ bit cell integration with copper interconnects", IEEE J. Solid-State Circuits, vol.38, p. 769, 2003.