CMOS shallow trench isolation x-stress effect on channel width for 0.18um technology

International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT

Volumn 1, Issue , 2004, Pages 319-320

  Tan, Philip Beow Yew ^a,b   Kordesch, Albert Victor ^a   Sidek, Othman ^b  

^a SILTERRA MALAYSIA SDN BHD   (Malaysia)

^b SCHOOL OF PHYSICS   (Malaysia)

Author keywords

[No Author keywords available]

Indexed keywords

COMPRESSIVE STRESS; DATA REDUCTION; FABRICATION; ION IMPLANTATION; MOSFET DEVICES; THRESHOLD VOLTAGE;

ELECTRICAL CHARACTERISTICS; NMOS TRANSISTORS; PMOS TRANSISTORS; SHALLOW TRENCH ISOLATION (STI);

CMOS INTEGRATED CIRCUITS;

EID: 21644470569     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. R. A. Bianchi et al., "Accurate Modeling of Trench Isolation Induced Mechanical Stress Effects on MOSFET Electrical Performance," International Electron Device Meeting, pp. 117 (2002).
2. M. Miyamoto et al., "Impact of Reducing STI-Induced Stress on Layout Dependence of MOSFET Characteristics," IEEE Transactions on Electron Devices, vol.51, no.3 (2004).
3. C. H. Ge et. al., "Process-Strained Si (PSS) CMOS Technology Featuring 3D Strain Engineering," International Electron Device Meeting, pp.73 (2003).