Clock switching: A new design for current testability (DcT) method for dynamic logic circuits

Proceeding - 1998 IEEE International Workshop on IDDQ Testing, IDDQ 1998

Volumn 1998-November, Issue , 1998, Pages 20-25

  Rosing, R ^a   Richardson, A M D ^a   Aimine, Y E ^a   Kerkhoff, H G ^b   Acosta, A J ^c  

^a LANCASTER UNIVERSITY   (United Kingdom)

^b UNIVERSITY OF TWENTE   (Netherlands)

^c INSTITUTO DE MICROELECTRÓNICA DE BARCELONA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL DETECTION; CLOCKS; LOGIC CIRCUITS; LOGIC DESIGN; TIMING CIRCUITS;

BRIDGING FAULT; CHARGE LEAKAGE; DOMINO LOGIC; DYNAMIC LOGIC; DYNAMIC LOGIC CIRCUITS; SINGLE PHASE; STATIC MODES; TEST METHODOLOGY;

COMPUTER CIRCUITS;

EID: 21644450966     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IDDQ.1998.730727     Document Type: Conference Paper

References (17)

1. R. Rajsuman, "Iddq Testing for CMOS VLSI", Artech House, Inc., 1995.
2. S. D. McEuen, "Reliability Benefits of Iddq", JETTA, 1992, pp. 41-48.
3. J.M. Soden, C.F. Hawkins, R.V. Gulati, W. Mao, "Iddq Testing: A review", JETTA, 1992, pp. 5-15.
4. R. Perry, "Iddq Testing in CMOS Digital ASICs", JETTA, 1992, pp. 31-39.
5. C.F. Hawkins, J.M. Soden, "Electrical Characteristics and Testing Considerations for Gate Oxide Shorts in CMOS Ics", Proceedings of the International Test Conference, 1985, pp. 544, 554.
6. C.F. Hawkins, J.M. Soden, A.W. Righter, F.J. Ferguson, "Defect Classes - An Overdue Paradigm for CMOS IC Testing", 1994, Proceedings of the International Test Conference, pp. 413-425.
7. J.A. Segura, V.H. Champac, R. Rodriguez-Montanes, J. Figueras, J.A. Rubio, "Quiescent Current Analysis and Experimentation of Defective CMOS Circuits", JETTA, 1992, pp. 51-62.
8. S.C. Ma and E.J. McClusky, "Design-for-Current Testability (DfCT) for Dynamic CMOS Logic", Centre for Reliable Computing, Technical Report No. 94-13, 1994.
9. H. Wunderlich, W. Rosentiel, "On Fault Modeling for Dynamic MOS Circuits", 23rd Design Automation Conference, 1986, pp. 540-547.
10. M. Singh, A. Arunachalam, "Non-classical Fault Detection in Dynamic CMOS", 22nd Asilomar Conference on Signals, Systems and Components, 1988, pp. 876-879.
11. R.H. Krambeck, C.M. Lee, H.S. Law, "High-Speed Compact Circuits with CMOS", IEEE Journal of Solid State Circuits, 1982, pp. 614-619.
12. R. Nicholson, A. Richardson, "Iddq Testable Dynamic CMOS", IEEE International Workshop on Iddq Testing, October 1995, pp.78-83.
13. J. Yuan, I. Karlsson, C. Svensson, "A True Single-Phase-Clock Dynamic CMOS Circuit Technique", IEEE Journal of Solid-State Circuits, 1987, pp. 899-901.
14. J. Yuan, C. Svensson, "High-Speed CMOS Circuit Technique", IEEE Journal of Solid-State Circuits, 1989, pp. 62-70.
15. R. Pereira, J.A. Michell and J.M. Solana, "Fully pipelined TSPC Barrel Shifter for High-Speed Applications", IEEE Journal of Solid-State Circuits, June 1995.
16. Q. Huang, R. Rogenmoser, "Speed Optimization of Edge-Triggered CMOS Circuits for Gigahertz Single-Phase Clocks", IEEE Journal of Solid-State Circuits, 1996, pp. 456-465.
17. R. Rodriguez-Montanes, E.M.J.G. Bruls, J. Figueras, "Bridging defects resistance measurements in a CMOS process", Proceedings of the International Test Conference, 1992, pp. 892-899.