CMOS downsizing toward sub-10 nm

Solid-State Electronics

Volumn 48, Issue 4, 2004, Pages 497-503

  Iwai, Hiroshi ^a  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

CMOS; Downsizing; MOSFETs; Scaling; Silicon; Transistor

Indexed keywords

GATES (TRANSISTOR); INTEGRATED CIRCUITS; LSI CIRCUITS; MICROPROCESSOR CHIPS; MOSFET DEVICES; MULTILAYERS; PROBLEM SOLVING; SILICON;

DOWNSIZING; SCALING;

CMOS INTEGRATED CIRCUITS;

EID: 0442296357     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2003.09.034     Document Type: Conference Paper

References (6)

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4. Mead C., Conway L. Introduction to VLSI systems. 1979;Addison Wesley, Reading, MA. p. 37.
5. Gelsinger PP. Microprocessor for the new millenium: challenges, opportunities, and new frontiers. In: Dig. Tech. 2001 IEEE International Solid-State Circuits Conference, February 2001, San Francisco. p. 22-3.
6. Ditzel DR. Transmeta's Crusoe: a low-power ×86-compatible microprocessor built with software. In: Proc. Cool Chips III, April 2000, Tokyo. p. 1-30.