Fourth-order PLL loop filter design technique with invariant natural frequency and phase margin

IEE Proceedings: Circuits, Devices and Systems

Volumn 152, Issue 2, 2005, Pages 103-108

  Thompson, I V ^a   Brennan, P V ^b  

^a Tait Electronics Ltd   (New Zealand)

^b UNIVERSITY COLLEGE LONDON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ATTENUATION; BANDWIDTH; CLOSED LOOP CONTROL SYSTEMS; COMPUTATIONAL METHODS; ELECTRIC FILTERS; NATURAL FREQUENCIES; THERMAL NOISE; TRANSFER FUNCTIONS;

FOURTH ORDER LOOPS; FREQUENCY OFFSETS; PHASE MARGIN; THIRD ORDER TIME CONSTANTS;

PHASE LOCKED LOOPS;

EID: 20444472806     PISSN: 13502409     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1049/ip-cds:20041201     Document Type: Conference Paper

References (8)

1. Brennan, P.V.: 'Phase-locked loops, principles and practice' (McGraw Hill, 1996)
2. Gardner, P.M.: 'Charge-pump phase-locked loops', IEEE Trans. Commun., November 1980, COM-28, pp. 1849-1858
3. Egan, W.F.: 'Frequency synthesis by phase lock' (Wiley-Interscience, 2000, 2nd edn.)
4. Best, R.E.: 'Phase-locked loops: theory, design, and applications' (McGraw Hill, 1993, 2nd edn.)
5. Banerjee, D.: 'PLL performance, simulation and design' (National Semiconductor, 2001, 2nd edn.), http://www.nsc.com/
6. Krug, F., and Wilwert, J.: 'Calculation and measurement of lock time in a phase-locked loop frequency synthesizer', Microw. J., April 2002, pp. 22-38
7. Stepinski, R.: 'Design high-order PLLs', Microw. RF, 2001, pp. 69-86
8. Thompson, I.: 'Strategies for the analysis and design of a low noise, frequency agile synthesiser'. PhD thesis. University College London, May 2003.