Design high-order PLLs

Microwaves and RF

Volumn 40, Issue 7, 2001, Pages

  Stepinski, Roman ^a  

^a Becker Electronics   (Poland)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 20444437560     PISSN: 07452993     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (7)

1. A.B. Przedpelski, "Optimize Phase-Lock Loops To Meet Your Needs - Or Determine Why You Can't," Electronic Design, September 13, 1978.
2. G. Nash, "Phase-Locked Loop Design Fundamentals," AN-535, Motorola.
3. F.M. Gardner, "Charge-Pump Phase-Lock Loops," IEEE Transactions On Communications, Vol. COM-28, No. 11, November 1980.
4. A. Blanchard, Phase locked loops, John Wiley & Sons, Inc., 1976.
5. A. Hodisan, Z. Hellman, and A. Brilliant, "Method Optimizes Performance of Phase-Locked Loops," Micrwaves & RF, September 1994.
6. U.L. Rohde, Microwave and Wireless Synthesizers - Theory and Design, John Wiley & Sons, 1997.
7. R. Stepinski, "Method For Reducing Active Filter Noise in PLL Synthesizers," Applied Microwave & Wireless, December 2000.