Experimental comparison between Double Gate, Ground Plane, and Single Gate SOI CMOSFETs

ESSCIRC 2004 - Proceedings of the 34th European Solid-State Device Research Conference

Volumn , Issue , 2004, Pages 77-80

  Lolivier, J ^a   Widiez, J ^b   Vinet, M ^a   Poiroux, T ^a   Dauge F ^c   Previtali, B ^a   Mouis, M ^c   Jommah, J ^c   Balestra, F ^c   Deleonibus, S ^a  

^a CEA LETI   (France)

^b STMICROELECTRONICS   (France)

^c IMEP LAHC   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CARRIER MOBILITY; CHEMICAL VAPOR DEPOSITION; COMPUTER SIMULATION; ELECTRIC FIELDS; ETCHING; GATES (TRANSISTOR); SILICON ON INSULATOR TECHNOLOGY; SUBSTRATES; SURFACE ROUGHNESS; THIN FILMS; THRESHOLD VOLTAGE;

GROUND PLANES (GP); PLANAR DOUBLE GATE (DG); SINGLE GATE (SG); THERMAL OXIDATIONS;

CMOS INTEGRATED CIRCUITS;

EID: 20244380175     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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