Body voltage and history effect sensitivity to key device parameters in 90nm PD-SOI

Proceedings - IEEE International SOI Conference

Volumn , Issue , 2004, Pages 19-20

  Kawanaka, S ^a   Ketchen, M B ^b   Bhushan, M ^b   Pearson, D J ^b   Bhasin, R ^c   Mcstay, K ^c   Sherony, M ^c   Fisher, P ^d   Matsumoto, K ^e   Utomo, H ^c   Nii, H ^a   Harifuchi, H ^e   Sudo, G ^a   Rausch, W ^c   Kimura, H ^e   Nakao, T ^a   Park, H ^c   Oh, S H ^c   Waite, A ^d   Womack, S ^c   Narasimha, S ^c   Mocuta, A C ^c   Ajmera, A ^c   Li, Y ^c,c   Malik, R ^c   Kohyama, Y ^a   Cheek, J ^d   Yang, I ^c   Clark, W F ^c   Divakaruni, R ^c   more..

^a Toshiba America Inc   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c IBM MICROELECTRONICS   (United States)

^d AMD Corporation   (United States)

^e SONY CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CONTROL SYSTEMS; DIODES; ELECTRIC POTENTIAL; LEAKAGE CURRENTS; MOSFET DEVICES; OPTIMIZATION; PHASE MODULATION; THIN FILMS;

DIODE CURRENT; HIGH DRAIN VOLTAGE; IMPLANTATION INDUCED DAMAGE (IID); POTENTIAL CHANGE;

SILICON ON INSULATOR TECHNOLOGY;

EID: 20144388033     PISSN: 1078621X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/soi.2004.1391537     Document Type: Conference Paper

References (4)

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3. M. Yoshimi, et al., IEDM Tech Digest, pp. 429-432, 1994.
4. F. Assaderaghi, et al., Symp. VLSI Tech., pp. 122-123, 1996.