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Volumn , Issue , 2004, Pages 405-408

A cost-efficient 0.18μm CMOS RF transceiver using a Fractional-N synthesizer for 802.11b/g wireless LAN applications

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; FREQUENCIES; ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING; PHASE LOCKED LOOPS; POWER AMPLIFIERS; SPURIOUS SIGNAL NOISE; THRESHOLD VOLTAGE; TRANSCEIVERS; WIRELESS TELECOMMUNICATION SYSTEMS;

EID: 20144387274     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (2)

References (6)
  • 2
    • 9144243660 scopus 로고    scopus 로고
    • A single-chip digitally calibrated 5.150Hz-5.825GHz 0.18μm CMOS transceiver for 802.11a wireless LAN
    • Dec.
    • Vassiliou, et al., "A single-chip digitally calibrated 5.150Hz-5.825GHz 0.18μm CMOS transceiver for 802.11a wireless LAN", IEEE J. Solid-State Circuits, vol. 38, No. 12, Dec. 2003, pp. 2221-2231.
    • (2003) IEEE J. Solid-State Circuits , vol.38 , Issue.12 , pp. 2221-2231
    • Vassiliou1
  • 3
    • 17044377218 scopus 로고    scopus 로고
    • A dual-band 5.15GHz-5.350Hz, 2.4GHz-2.5GHz, 0.18μm CMOS traniceiver for 802.11a/b/g wirelen LAN
    • to appear in
    • K. Vavelidil, et al., "A Dual-Band 5.15GHz-5.350Hz, 2.4GHz-2.5GHz, 0.18μm CMOS Traniceiver for 802.11a/b/g Wirelen LAN", to appear in IEEE J. Solid-State Circuits.
    • IEEE J. Solid-state Circuits
    • Vavelidil, K.1
  • 4
    • 0031211646 scopus 로고    scopus 로고
    • New methods for adaptation of quadrature modulators and demodulators in amplifier linearization circuits
    • Aug.
    • J. K. Cavers, "New methods for adaptation of quadrature modulators and demodulators in amplifier linearization circuits", IEEE Trans. on Vehicular Technology, vol. 46, no. 3, pp. 707-716, Aug. 1997.
    • (1997) IEEE Trans. on Vehicular Technology , vol.46 , Issue.3 , pp. 707-716
    • Cavers, J.K.1
  • 5
    • 0027634063 scopus 로고
    • The basis and architecture for the reduction of tones in a sigma-delta DAC
    • July
    • R. C. Ledzius, J. Irwin, "The Basis and Architecture for the Reduction of Tones in a Sigma-Delta DAC", IEEE Trans. on Circuit and Systems-11, vol. 40, No. 7, July 1993, pp. 429-439.
    • (1993) IEEE Trans. on Circuit and Systems-11 , vol.40 , Issue.7 , pp. 429-439
    • Ledzius, R.C.1    Irwin, J.2
  • 6
    • 0004121923 scopus 로고    scopus 로고
    • J. Wiley & Sons Inc.
    • nd ed., J. Wiley & Sons Inc., 2000.
    • (2000) nd Ed.
    • Egan, W.F.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.