Investigation of poly-Si/HfO2 gate stacks in a self-aligned 70nm MOS process flow

European Solid-State Device Research Conference

Volumn , Issue , 2003, Pages 251-254

  Kubicek, S ^a   Chen, J ^a   Ragnarsson, L A ^a   Carter, R J ^a   Kaushik, V ^a   Lujan, G S ^a   Cartier, E ^a   Henson, W K ^a   Kerber, A ^a   Pantisano, L ^a   Beckx, S ^a   Jaenen, P ^a   Boullart, W ^a   Caymax, M ^a   Degendt, S ^a   Heyns, M ^a   De Meyer, K ^a,b  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

GATE STACKS; PROCESS FLOWS; SELF-ALIGNED;

EID: 20044386766     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2003.1256861     Document Type: Conference Paper

References (8)

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3. R. Carter et al., APL submitted for the publication
4. J. R. Hauser et. al., Characterization and Metrology for ULSI Technology: Int. Conf., p. 235 (1998).
5. Y. Taur, T. Ning: Fundamentals of Modem VLSI devices, CUP 1998
6. M. Fischetti et. al, Journal of Applied Physics, Vol. 90, Number 9, Nov. 2001, pp.4587
7. S. Saito et. al., VLSI 2001
8. G. Lujan et al.: submitted to this conference