Novel fabrication process to realize ultra-thin (EOT = 0.7 nm) and ultra-low-leakage SiON gate dielectrics

Microelectronic Engineering

Volumn 80, Issue SUPPL., 2005, Pages 424-431

  Matsushita, D ^a   Muraoka, K ^a   Kato, K ^a   Nakasaki, Y ^a   Inumiya, S ^a   Eguchi, K ^a   Takayanagi, M ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

First principles calculations; I V method; SiN base SiON; SiON

Indexed keywords

AGGLOMERATION; CURRENT VOLTAGE CHARACTERISTICS; DEGRADATION; DIELECTRIC FILMS; LEAKAGE CURRENTS; OXIDATION RESISTANCE; PERMITTIVITY;

FIRST PRINCIPLES CALCULATIONS; I-V METHOD; NITRIDATION; SIN BASE SION; SION;

ULTRATHIN FILMS;

EID: 19944398154     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2005.04.099     Document Type: Conference Paper

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