PVD-HfSiON gate dielectrics with Ni-FUSI electrode for 65nm LSTP application

Microelectronic Engineering

Volumn 80, Issue SUPPL., 2005, Pages 198-201

  Yamamoto, K ^a   Kubicek, S ^b   Rothschild, A ^b   Mitsuhashi, R ^a   Deweerd, W ^b   Veloso, A ^b   Jurczak, M ^b   Biesemans, S ^b   De Gendt, S ^b,c   Wickramanayaka, S ^d   Hayashi, S ^e   Niwa, M ^a  

^a IMEC   (Belgium)

^b CMOS Device Research Group   (Belgium)

^c UNIVERSITY OF LEUVEN   (Belgium)

^d Canon ANELVA Technix Corporation   (Japan)

^e PANASONIC CORPORATION   (Japan)

Author keywords

FUSI; Hafnium oxide; HfSiON; High k gate; Oxidation; Physical vapor deposition

Indexed keywords

FUSI; HAFNIUM OXIDE; HFSION; HIGH-K GATE;

CAPACITANCE; CHEMICAL MECHANICAL POLISHING; ELECTRODES; HAFNIUM COMPOUNDS; HEAT TREATMENT; LEAKAGE CURRENTS; OXIDATION; PERMITTIVITY; PHYSICAL VAPOR DEPOSITION;

DIELECTRIC FILMS;

EID: 19944375496     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2005.04.068     Document Type: Conference Paper

References (5)

1. K. Yamamoto, S. Hayashi, M. Niwa, M. Asai, S. Horii, and H. Miya Appl. Phys. Lett. 83 2003 2229
2. B. Tavel, T. Skotnicki, G. Pares, N. Carriere, M. Rivoire, F. Leverd, C. Julien, J. Torres, and R. Pantel IEDM Tech. Dig. 2001 825
3. K.G. Anil, A. Veloso, S. Kubicek, T. Schram, E. Augendre, J.F. de Marneffe, K. Devriendt, A. Lauwers, S. Brus, K. Henson, and S. Biesmans Symp. VLSI Tech. Dig. 2004 190
4. Y. Morisaki, T. Aoyama, Y. Sugita, K. Irino, T. Sugii, and T. Nakamura IEDM Tech. Dig. 2002 861
5. M. Koyama, A. Kaneko, T. Ino, M. Koike, Y. Kamata, R. Iijima, Y. Kamimuta, A. Takashima, M. Suzuki, C. Hongo, S. Inumiya, M. Takayanagi, and A. Nishiyama IEDM Tech. Dig. 2002 849