A physical analytical model of multilayer on-chip inductors

IEEE Transactions on Microwave Theory and Techniques

Volumn 53, Issue 4 I, 2005, Pages 1143-1148

  Tong, K Y ^a   Tsui, C ^a  

^a HONG KONG POLYTECHNIC UNIVERSITY   (Hong Kong)

Author keywords

Eddy currents; Inductor model; On chip inductors; RF integrated circuits (ICs)

Indexed keywords

CMOS INTEGRATED CIRCUITS; EDDY CURRENTS; MICROPROCESSOR CHIPS; MULTILAYERS; NATURAL FREQUENCIES; SILICON; SUBSTRATES;

EDDY-CURRENT LOSSES; INDUCTOR MODEL; ON-CHIP INDUCTORS; RF INTEGRATED CIRCUITS (IC);

ELECTRIC INDUCTORS;

EID: 18744396375     PISSN: 00189480     EISSN: None     Source Type: Journal    
DOI: 10.1109/TMTT.2005.845721     Document Type: Article

References (17)

1. S. P. Yue and S. S. Wong, "Physical modeling of spiral inductors on silicon," IEEE Trans. Electron Devices, vol. 47, no. 3, pp. 560-568, Mar. 2000.
2. A. M. Niknejad and R. G. Meyer, "Analysis of eddy-current losses over conductive substrates with applications to monolithic inductors and transformers," IEEE Trans. Microw. Theory Tech., vol. 49, no. 1, pp. 166-176, Jan. 2001.
3. B. A. Floyd, C. M. Hung, and K. K. O, "The effects of substrate resistivity on RF component and circuit performance," in Proc. Int. Interconnect Technology Conf., 2000, pp. 164-166.
4. M. Ozgur, M. E. Zaghloul, and M. Gaitan, "Optimization of backside micromachined CMOS inductors for RF applications," in Proc. IEEE Int. Circuits Systems Symp., vol. 5, May 2000, pp. 185-188.
5. A. M. Niknejad and R. G. Meyer, "Analysis, design and optimization of spiral inductors and transformers for Si RF ICs," IEEE J. Solid-State Circuits, vol. 33, no. 10, pp. 1470-1481, Oct. 1998.
6. G. Grau, U. Langmann, W. Winkler, D. Knoll, and K. Pressel, "A 5.8 GHz Si/SiGe VCO with amplitude control for wireless LAN applications," IEICE Trans. Electron., vol. E84-C, pp. 1437-1441, Oct. 2001.
7. J. Sieiro, J. M. Lopez-Villegas, J. Cabanillas, J. A. Osoriao, and J. Samitier, "A physical frequency-dependent compact model for RF integrated inductors," IEEE Trans. Microw. Theory Tech., vol. 50, no. 1, pp. 384-392, Jan. 2002.
8. J. M. Lopez-Villegas, J. Samitier, C. Cane, and P. Losantos, "Improvement of the quality factor of RF integrated inductors by layout optimization." IEEE Trans. Microw. Theory Tech., vol. 48, no. 1, pp. 76-83, Jan. 2000.
9. W. B. Kuhn and N. M. Ibrahium, "Analysis of current crowding effects in multiturn spiral inductors," IEEE Trans. Microw. Theory Tech., vol. 49, no. 1, pp. 166-176, Jan. 2001.
10. S. S. Mohan, M. M. Hershenson, S. P. Boyd, and T. H. Lee, "Simple accurate expressions for planar spiral inductors," IEEE J. Solid-State Circuits, vol. 32, no. 3, pp. 357-369, Mar. 1997.
11. J. R. Long and M. A. Copeland, "The modeling, characterization and design of monolithic inductors for silicon RF ICs," IEEE J. Solid-State Circuits, vol. 32, no. 3, pp. 357-369, Mar. 1997.
12. W. C. Wu, Y. J. Chan, and C. K. Wang, "An enhanced model for planar inductors in CMOS technology," in Int. VLSI Technology, Systems, Applications Symp., 1999, pp. 143-146.
13. J. R. Long and M. Danesh, "A uniform compact model for planar RF/MMIC interconnect, inductors and transformers," in Proc. Bipolar/BiCMOS Circuits Technology Meeting, Oct. 2001, pp. 167-170.
14. A. Zolfaghari, A. Chan, and B. Razavi, "Stacked inductors and transformers in CMOS technology," IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 620-627, Apr. 2001.
15. C. C. Tang, C. H. Wu, and S. I. Liu, "Miniature 3-D inductors in standard CMOS process," IEEE J. Solid-State Circuits, vol. 37, no. 4, pp. 471-479, Apr. 2002.
16. F. W. Grover, Inductance Calculations. New York: Dover, 1962.
17. E. Pettenpaul, H. Kapusta, A. Weisgerber, H. Mampe, J. Luginsland, and I. Wolff, "CAD models of lumped elements on GaAs up to 18 GHz," IEEE Trans. Microw. Theory Tech., vol. 36, no. 2, pp. 294-304 Feb. 1988.