Hardware-in-the-loop evolution of a 3-bit multiplier

Proceedings - 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2004

Volumn , Issue , 2004, Pages 277-278

  Larchev, Gregory V ^a   Lohn, Jason D ^a  

^a NASA AMES RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FAULT ISOLATION; FAULT-REPAIR ALGORITHMS; FEEDBACK LOOPS; GENETIC PROGRAMMING;

COMPUTER SIMULATION; COMPUTER SOFTWARE; EVOLUTIONARY ALGORITHMS; FAULT TOLERANT COMPUTER SYSTEMS; FEEDBACK; FIELD PROGRAMMABLE GATE ARRAYS; FIR FILTERS; GENETIC ALGORITHMS; JAVA PROGRAMMING LANGUAGE; OPTIMIZATION; REAL TIME SYSTEMS; REDUNDANCY; SIGNAL PROCESSING; SPACE APPLICATIONS;

COMPUTER HARDWARE;

EID: 18644381370     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FCCM.2004.39     Document Type: Conference Paper

References (4)

1. J.Lohn, G.Larchev, R.DeMara, "A Genetic Representation for Evolutionary Fault Recovery in Virtex FPGAs," in Proceedings of Evolvable Systems: From Biology to Hardware, 5th International Conf., ICES 2003, March 2003, Trondheim, Norway.
2. J.F.Miller, M. Hartmann, "Evolving messy gates for fault tolerance: some preliminary findings," in Proceedings of the Third NASA/DOD Workshop on Evolvable Hardware, July 12-14, 2001, Long Beach, CA.
3. A.Thompson, "Silicon Evolution," in Proceedings of Genetic Programming Conference 1996, July 28-31, 1996, Stanford, CA.
4. V.K.Vassilev, D.Job and J.F.Miller, "Towards the Automatic Design of More Efficient Digital Circuits," in Proceedings of The Second NASA/DOD Workshop on Evolvable Hardware, July 13-15, 2000, Palo Alto, CA.