Open architecture test system: System architecture and design

Proceedings - International Test Conference

Volumn , Issue , 2004, Pages 403-412

  Rajsuman, Rochit ^a   Noriyuki, Masuda ^b  

^a Advantest America Corporation   (United States)

^b ADVANTEST CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMMUNICATION; COMPUTER SOFTWARE; ELECTRIC POTENTIAL; INTEGRATED CIRCUITS; REENGINEERING; SIGNAL PROCESSING; THROUGHPUT; WAVEFORM ANALYSIS;

CONTROL ELEMENTS; OPEN ARCHITECTURE SYSTEM DESIGN; SYSTEM ARCHITECTURE; TEST EQUIPMENT;

SYSTEMS ANALYSIS;

EID: 18144364384     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. International Technology Roadmap for Semiconductor (ITRS Roadmap), Sematech, Nov. 2003.
2. S. Ferez and Y. Furukawa, "Open Architecture Test System: The new frontier", Semi Technology Symposium, Semicon West, 2003.
3. S. Sugamori and R. Rajsuman, "Module based flexible semiconductor test system", US Patent Number 6,623,282, Sep. 30, 2003.
4. R. Rajsuman, "Open architecture ATE tackles test woes", EE Times, Oct. 24, 2003.
5. R. Rajsuman, "Open ATE platform must support parallel test", EE Times, July 21, 2003.
6. OPENSTAR™ Specifications, Semiconductor Test Consortium, 2003.
7. R. Rajsuman, "The nuts and bolts of the open architecture test system", Semiconductor Manufacturing, pp. 80-86, March 2004.
8. R. Rajsuman, "An overview of the open architecture test system", IEEE Int. Wks on Electronic Design, Test and Applications (DELTA), pp. 341-346, 2004.
9. OPENSTAR™ bus specifications, Semiconductor Test Consortium, Nov. 2003.
10. P. Kruchten, "The rational unified process", Addison Wesley, 1998.