An overview of the open architecture test system

Proceedings, DELTA 2004 - Second IEEE International Workshop on Electronic Design, Test and Applications

Volumn , Issue , 2004, Pages 341-346

  Rajsuman, Rochit ^a  

^a Advantest America R and D Center   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TEST EQUIPMENT (ATE); DEVICE-UNDER-TEST (DUT); SYSTEM-ON-A-CHIP (SOC);

AUTOMATIC TESTING; COMPUTER HARDWARE; COMPUTER PROGRAMMING; COSTS; DATA REDUCTION; EQUIPMENT TESTING;

COMPUTER SOFTWARE;

EID: 4544231219     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DELTA.2004.10026     Document Type: Conference Paper

References (5)

1. International Technology Roadmap for Semiconductor (ITRS Roadmap), to be released in Nov. 2003, Sematech.
2. R. Rajsuman, "Open architecture ATE tackles test woes", EE Times, Oct. 24, 2003.
3. Yasuo Furukawa and Sergio Ferez, "Open Architecture Test System: The new frontier", Semi Technology Symposium, Semicon West, 2003.
4. OPENSTAR™ Specifications, Semiconductor Test Consortium, 2003.
5. R. Rajsuman, "Open ATE platform must support parallel test", EE Times, July 21, 2003.