The time-voltage trade-off for ESD damage threshold in amorphous silicon hydrogenated thin-film transistors

Microelectronics Reliability

Volumn 41, Issue 9-10, 2001, Pages 1391-1396

  Golo, N Tošić ^a   Van Der Wal, S ^b   Kuper, F G ^a,b   Mouthaan, T ^a  

^a UNIVERSITY OF TWENTE   (Netherlands)

^b NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

AMORPHOUS SILICON; COMPUTER SIMULATION; ELECTRIC BREAKDOWN; ELECTRIC DISCHARGES; ELECTRIC POTENTIAL; GATES (TRANSISTOR);

ELECTROSTATIC DISCHARGES (ESD);

THIN FILM TRANSISTORS;

EID: 18044364988     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(01)00148-2     Document Type: Article

References (6)

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2. Maloney T. J., Khurana N. TLP techniques for circuits modeling of ESD phenomena. Proc. of EOS/ESD Symp. (1985) 49-54.
3. Dwyer V. M., Franklin A. J., Campbell D. S. Thermal failure in semiconductor devices. Solid State Electronics, Vol. 33, No. 5 (1990) pp. 553-560.
4. Tada M., Uchikoga S., Ikeda M. Power-density-dependent failure of amorphous-Si TFT. AMLCD Proc. (1996) pp. 269-272.
5. Tai Y. H., Tsai J. W., Cheng H. C., Su F. C. Anomalous bias-stress-induced unstable phenomena of hydrogenated amorphous silicon thin film transistors. Applied Physics Letters, Vol. 67, No. 1 (1995) pp.76-78.
6. Kaneko Y., Sasano A., Tsukada T. Characterization of instability in a-Si TFTs. Journ. Appl. Phys., Vol. 69, No. 10 (1991) pp. 7301-7305.