Fully Compatible Integration of High Density Embedded DRAM with 65nm CMOS Technology (CMOS5)

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2003, Pages 423-426

  Matsubara, Y ^a   Habu, M ^a   Matsuda, S ^a   Honda, K ^a   Morifuji, E ^a   Yoshida, T ^a   Kokubun, K ^a   Yasumoto, K ^a   Sakurai, T ^a   Suzuki, T ^a   Yoshikawa, J ^a   Takahashi, E ^a   Hiyama, K ^a   Kanda, M ^a   Ishizuka, R ^a   Moriuchi, M ^a   Koga, H ^b   Fukuzaki, Y ^b   Sogo, Y ^b   Takahashi, H ^b   Nagashima, N ^b   Okamoto, Y ^b   Yamada, S ^a   Noguchi, T ^a   more..

^a TOSHIBA CORPORATION   (Japan)

^b SONY CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BORON; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC FIELDS; GATES (TRANSISTOR); ION IMPLANTATION; LEAKAGE CURRENTS; MOSFET DEVICES; SEMICONDUCTOR JUNCTIONS; TRANSMISSION ELECTRON MICROSCOPY;

JUNCTION LEKAKAGE; SALICIDE BLOCK TECHNOLOGY;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 17644449166     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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4. A. Kajita, et al., Proc. IITC, p. 9, 2003.
5. M. Kanda, et al., Symp. on VLSI Tech., p. 13, 2003.
6. E. Morifuji, et al., Proc. IEDM, p. 655, 2002.
7. K. Kokubun, et al., Symp. on VLSI Tech., p. 155,1999.