Interface passivation mechanisms in metal gated oxide capacitors

ESSCIRC 2004 - Proceedings of the 34th European Solid-State Device Research Conference

Volumn , Issue , 2004, Pages 325-328

  Lujan, G S ^a,b   Schram, T ^a   Sjoblom, G ^a,c   Witters, T ^a   Kubicek, S ^a   De Gendt, S ^a,b   Heyns, M ^a   De Meyer, K ^a,b  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

^c UPPSALA UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; DATA REDUCTION; ELECTRIC POTENTIAL; INTEGRATION; MATHEMATICAL MODELS; MOSFET DEVICES; PASSIVATION;

CONDUCTANCE TECHNIQUES; GATE VOLTAGES; HYDROGEN DIFFUSION; POLY ELECTRODES;

MOS CAPACITORS;

EID: 17644392496     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. W. Tsai, et al., IEDM technical digest, p. 311, 2003
2. C. Hobbs, VLSI 2003 pp.2.
3. R. J. Carter, E. Cartier, A. Kerber, L. Pantisano, T. Schram, S. De Gendt, and M. Heyns, Applied Physics Letters, Vol. 83, No. 3, pp. 533, 2003
4. E.H. Nicollian, A. Goetzberger, A. D. Lopez, Solid State Electronics, Vol. 12, 1969, pp. 937.
5. E.H. Nicollian, A. Goetzberger, Bell System Technology Journal, Vol. 46, 1967, pp. 1055.