Design and implementation of scalable low-power Montgomery multiplier

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2004, Pages 524-531

  Son, Hee Kwan ^a   Oh, Sang Geun ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DATA PROCESSING; DATA STORAGE EQUIPMENT; DATA TRANSFER; ELECTRIC POTENTIAL; ENERGY UTILIZATION; ERROR ANALYSIS;

CARRY-SAVE ADDER (CSA); EXPECTED SWITCHING ACTIVITY (ESA); LOGIC SIMULATION; METAL LAYERS; MULTIPLIERS;

COMPUTER AIDED DESIGN;

EID: 17644376616     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

1. R.L. Rivest, A. Sharmir, and L. Adleman, "A Method of Obtaining Digital Signature and Public-Key Cryptosystems," Comm. ACM., vol. 21, no. 2, pp. 120-126, 1982
2. W. Diffie and M.E. Hellman, "New Directions in Cryptography," IEEE Trans. Information Theory, vol. 22, pp. 644-654, 1976
3. P.L. Montgomery, "Modular Multiplication without Trial Division," Math. Computing, vol. 44, no. 170, pp. 519-521, Apr. 1985
4. J. Menezes, P.C. van Oorschot, and S.A. Vanstone, Handbook of Applied Cryptography, CRC Press, 1997
5. C. Walter, "Systolic Modular Multiplication," IEEE Trans. Computers, vol. 42, no. 3, pp. 376-378, Mar. 1993
6. P. Kornerup, "A Systolic, Linear-Array Multiplier for a Class of Right-Shift Algorithms," IEEE Trans. Computers, vol. 43, no. 8, pp. 892-898, Aug. 1994
7. W.C. Tsai, C.B. Shung, and S.J. Wang, "Two Systolic Architecture for Modular Multiplication,", IEEE Trans. VLSI, vol. 8, no. 1, pp. 103-107, Feb. 2000
8. A.F. Tenca and C.K. Koc, "A Scalable Architecture for Modular Multiplication Based on Montgomery's Algorithm," IEEE Trans. Computers, vol. 52, no.9, pp. 1215-1221, Sep. 2003
9. A.F. Tenca and C.K. Koc, "High-Radix Design of a Scalable Modular Multiplier," Proc. Cryptographic Hardware and Embedded Systems (CHES 2001), pp. 189-205, May 2001
10. J.J. Leu and A.Y. Wu, "Design Methodology for Booth-Encoded Montgomery Module Design for RSA Cryptpsystem," Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2000), pp. V.357-360, May 2000
11. J.H. Hong and C.W. Wu, "Radix-4 Modular Multiplication and Exponentiation Algorithm for the RSA Public-key Cryptosystem," ASP-DAC, pp. 565-570, 2000
12. S.F. Hsiao, M.R. Jiang and J.S. Yeh, "Design of high-speed low-power 3-2 counter and 4-2 compressor for fast multipliers," Electronics Letters, vol. 34, no. 4, pp. 341-343, Feb. 1998
13. th Symp. Computer Arithmetic, pp. 193-199, July 1995