Vlsi architecture and FPGA implementation of ICE encryption algorithm

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 1, Issue , 2003, Pages 88-91

  Fournaris, A P ^a   Sklavos, N ^a   Koufopavlou, O ^a  

^a UNIVERSITY OF PATRAS   (Greece)

Author keywords

[No Author keywords available]

Indexed keywords

CRYPTOGRAPHIC ALGORITHMS; ENCRYPTION ALGORITHMS; ENCRYPTION AND DECRYPTION; FPGA DEVICES; FPGA IMPLEMENTATIONS; HARDWARE ARCHITECTURE; HARDWARE IMPLEMENTATIONS; HIGH-SPEED PERFORMANCE; PROPOSED ARCHITECTURES; SYSTEM CLOCK; VLSI ARCHITECTURES; FOLDED ARCHITECTURES;

ALGORITHMS; HARDWARE; VLSI CIRCUITS; CRYPTOGRAPHY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

CRYPTOGRAPHY; ALGORITHMS;

EID: 17444423868     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2003.1301983     Document Type: Conference Paper

References (12)

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2. M. Kwan, "The Design of the ICE Encryption Algorithm," in Proc. of Fast Software Encryption Workshop, 1997.
3. A. A. Moldovyan and N. A. Moldovyan, "A cipher Based on Data - Dependent Permutations", Journal of Cryptology, no.15, pp 61 - 72, 2002.
4. Nick D. Goots, Alexander A. Moldovyan, Nick A. Moldovyan, "Fast Encryption Algorithm SPECTR - H64", in Proc. Of International Workshop on Mathematical Methods, Models and Architectures for Computer Networks Security, (MMM-ACNS'01), Russia, May 2001, Springer - Verlag, pp. 275-286
5. D.J. Guan, Montgomery Algorithm for Modular Multiplication, Lecture notes, National Sun Yat Sen University, 2001.
6. Peter L. Montgomery, "Modular multiplication without trial division," Mathematics of Computation, vol.44, no.170, pp. 519-521, 1985.
7. T.H. Cormen, C.E. Leiserson, and R.L. Rivest, Introduction to Algorithms, The MIT Press, Cambridge, 1990.
8. Shay Gueron, "Enhanced Montgomery Multiplication," in Proc. of Workshop on Cryptographic Hardware and Embedded Systems, San Francisco, August 13-15 2002.
9. K. Gaj and P. Chodowiec, "Comparison of the Hardware Performance of the AES Candidates Using Reconfigurable Hardware," in proc. Of Third Advanced Encryption Standard (AES) Candidate Conf Apr. 2000.
10. R. Zimmermann, A. Curiger, H. Bonnenberg, H. Kaeslin, N. Felber, and W.Fichtner, "A 177Mb/s VLSI Implementation of the International Data Encryption Algorithm", IEEE Journal of Solid-State Circuits, vol.29, no.3, pp 303 - 307, 1994.
11. N. Sklavos, A. A. Moldovyan, and O. Koufopavlou, "Encryption and Data Dependent Permutations: Implementation Cost and Performance Evaluation", proceedings of International Workshop on Mathematical Methods, Models and Architectures for Computer Networks Security, (MMM-ACNS'03), Springer-Verlag, Berlin 2003.
12. Taek-Won Kwan, Chang-Seok You, Won-Seok Heo, Yong-Kyu Kang, and Jun-Rim Choi, "Two implementation methods of a 1024-bit RSA cryptoprocessor Based on Modified Montgomery Algorithm", proceedings of 2001 IEEE ISCAS '01, May 6-9, Sydney, Australia.