Software pipelining irregular loops on the TMS320C6000 VLIW DSP architecture

SIGPLAN Notices (ACM Special Interest Group on Programming Languages)

Volumn 36, Issue 8, 2001, Pages 138-144

  Granston, Elana ^a   Stotzer, Eric ^a   Zbiciak, Joe ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

Algorithms; D.3.4 Programming Languages : Processors code generation, compilers, optimization; Design; Digital Signal Processors; Management; Performance; Software pipelining; VLIW architectures; WHILE loops

Indexed keywords

EID: 17244367211     PISSN: 03621340     EISSN: None     Source Type: Journal    
DOI: 10.1145/384196.384216     Document Type: Article

References (11)

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