A 0.13-μm CMOS 5-Gb/s 10-meter 28AWG cable transceiver with no-feedback-loop continuous-time post-equalizer

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2002, Pages 64-67

  Kudoh, Yoshiharu ^a   Fukaishi, Muneo ^a   Mizuno, Masayuki ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); ATTENUATION EQUALIZERS; MICROELECTRONICS; NATURAL FREQUENCIES;

CABLE TRANSCEIVER; CONTINUOUS TIME POST EQUALIZER; HIGH SPEED ANALOG AMPLIFIERS;

CMOS INTEGRATED CIRCUITS;

EID: 0141498615     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. W. J. Dally et al., "Transmitter Equalization for 4-Gbps Signaling," 1997 IEEE Micro, pp. 48-56.
2. M. E. Lee et al., "A 90-mW 4-Gb/s Equalized I/O Circuit with Input Offset Cancellation," 2000 IEEE ISSCC, pp. 252-253.
3. J. N. Babenezhad, "A 3.3-V Analog Adaptive Line-Equalizer for Fast Ethernet Data Connection," 1998 IEEE CICC, pp. 343-346.
4. K. Gotoh et al., "A 2B Parallel 1.25-Gb/s Interconnect I/O Interface with Self-Configurable Link and Plesiochronous Clocking," 1999 IEEE ISSCC, pp. 180-181.
5. J. Sim et al., "840-Mbs CMOS Demultiplexed Equalizing Transceiver for DRAM-to-Processor Communication," 1999 Symp. on VLSI circuits, pp. 23-24.
6. K. Tanaka et al., "A 100-Gb/s Transceiver with GND-VDD Common-Mode Receiver and Flexible Multi-Channel Aligner," 2002 IEEE ISSCC, to be published.