Customisable hardware compilation

Journal of Supercomputing

Volumn 32, Issue 2, 2005, Pages 119-137

  Todman, Tim ^a   Coutinho, José Gabriel De F ^a   Luk, Wayne ^a  

^a IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

Hardware compilation; High level design; Pipelining

Indexed keywords

ALGORITHMS; HIGH LEVEL LANGUAGES; OPTIMIZATION; PRODUCTIVITY; PROGRAM COMPILERS; SCHEDULING; SIGNAL PROCESSING;

HARDWARE COMPILATION; HIGH-LEVEL DESIGN; HIGH-LEVEL SYNTHESIS; PIPELINING;

COMPUTER HARDWARE;

EID: 17044415218     PISSN: 09208542     EISSN: None     Source Type: Journal    
DOI: 10.1007/s11227-005-0288-x     Document Type: Article

References (22)

1. A. Abdul Gaffar et al. Unifying bit-width optimisation for fixed-point and floating-point designs. In IEEE Symp. on Field-Programmable Custom Computing Machines, IEEE Computer Society Press, 2004.
2. A. Aho, R. Sethi, and J. Ullman. Compilers: Principles, Techniques, and Tools. Series in Computer Science, Addison-Wesley, 1986.
3. ANTLR, wwv.antlr.org.
4. M. Boekhold et al. A programmable ANSI C transformation engine. In Proc. Int. Conf. on Compiler Construction, LNCS 1575, Springer, 1999.
5. Celoxica, www.celoxica.com.
6. J. G. F. Coutinho and W. Luk. Source-directed transformations for hardware compilation. In Proc. Int. Conf. on Field-Programmable Technology, IEEE, 2003.
7. J. G. F. Coutinho, W. Luk, and M. Weinhardt. Optimizing parallel programs for hardware implementation. In Proc. SPIE ITCom, 2002.
8. G. De Micheli. Synthesis and Optimization of Digital Circuits. McGraw-Hill, 1994.
9. E. Gamma, R. Helm, R. Johnson, and J. Vlissides. Design Patterns: Elements of Reusable Object-Oriented Software. Addison-Wesley, 1995.
10. M. B. Gokhale et al. Stream-oriented FPGA computing in the Streams-C high level language. In IEEE Symp. on Field-Programmable Custom Computing Machines, IEEE Computer Society Press, 2000.
11. S. Gupta et al. SPARK: A high-level synthesis framework for applying parallelizing compiler transformations. In Proc. Int. Conf. on VLSI Design, Jan. 2003.
12. T. K. Lee et al. Compiling policy descriptions into reconfigurable firewall processors. In Proc. Symp. on Field-Programmable Custom Computing Machines, IEEE Computer Society Press, 2003.
13. W. Luk and S. W. McKeever. Pebble: A language for parametrised and reconfigurable hardware design. Field-Programmable Logic and Applications, LNCS 1482, Springer, 1998.
14. S. W. McKeever and W. Luk. Towards provably-correct hardware compilation tools based on pass separation techniques. Correct Hardware Design and Verification Methods, LNCS 2144, Springer, 2001.
15. O. Mencer et al. Design space exploration with A Stream Compiler. In Proc. Int. Conf. on Field Programmable Technology, IEEE, 2003.
16. S. Meyers. Effective C++, 2nd ed. Addison-Wesley, 1998.
17. I. Page and W. Luk. Compiling occam into FPGAs. FPGAs, Abingdon EE&CS Books, 1991.
18. N. Shirazi, W. Luk, and P. Y. K. Cheung. Framework and tools for run-time reconfigurable designs. In IEE Proc.-Computing and Digital Techniques, May, 2000.
19. SUIF Compiler System, suif. Stanford. edu.
20. T. Todman. A customisable framework for hardware compilation. PhD thesis, Imperial College, 2003.
21. T. Todman and W. Luk. Combining imperative and declarative hardware descriptions. In Proc. 36th Hawaii Int. Conf. on System Sciences, IEEE, 2003.
22. M. Weinhardt and W. Luk. Pipeline vectorization. IEEE Trans. on Computer-Aided Design, 20(2), 2001.