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Volumn , Issue , 2004, Pages 39-42

A 10Gb/s data-dependent jitter equalizer

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; BIT ERROR RATE; CMOS INTEGRATED CIRCUITS; DATA COMMUNICATION SYSTEMS; DATA REDUCTION; DIFFERENTIATION (CALCULUS); EQUALIZERS; MATHEMATICAL MODELS; SPURIOUS SIGNAL NOISE;

EID: 17044398451     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (13)

References (9)
  • 1
    • 17044429509 scopus 로고    scopus 로고
    • Fibre channel - Methodologies for Jitter and Signal Quality specification- MJSQ
    • March 10
    • International Committee for Information Technology Standardization (INCITS), Fibre Channel - Methodologies for Jitter and Signal Quality Specification- MJSQ, Technical Report REV 10.0, March 10, 2003.
    • (2003) Technical Report REV 10.0
  • 5
    • 0036858189 scopus 로고    scopus 로고
    • Jitter optimization based on phase-locked loop design parameters
    • Nov.
    • M. Mansuri and C.-K. K. Yang, "Jitter Optimization Based on Phase-Locked Loop Design Parameters," IEEE Journal of Solid-State Circuits, vol. 37, pp. 1375-1382, Nov. 2002.
    • (2002) IEEE Journal of Solid-state Circuits , vol.37 , pp. 1375-1382
    • Mansuri, M.1    Yang, C.-K.K.2
  • 7
    • 0022187594 scopus 로고
    • A self-correcting clock recovery circuit
    • Dec.
    • C. R. Hogge, "A Self-Correcting Clock Recovery Circuit," IEEE Journal of Lightwave Technology, vol. 3, pp. 1312-1314, Dec. 1985.
    • (1985) IEEE Journal of Lightwave Technology , vol.3 , pp. 1312-1314
    • Hogge, C.R.1
  • 8
    • 85008057622 scopus 로고    scopus 로고
    • A versatile clock recovery architecture and monolithic implementation
    • B. Razavi, Ed., New York: IEEE Press
    • L. DeVito, "A Versatile Clock Recovery Architecture and Monolithic Implementation," Monolithic Phase-Locked Loops and Clock Recovery Circuits, B. Razavi, Ed., New York: IEEE Press, 1996.
    • (1996) Monolithic Phase-locked Loops and Clock Recovery Circuits
    • DeVito, L.1
  • 9
    • 0026996358 scopus 로고
    • A 155 MHz clock recovery delay-and phase-locked loop
    • Dec.
    • T. H. Lee and J. F. Bulzacchelli, "A 155 MHz Clock Recovery Delay-and Phase-Locked Loop," IEEE Journal of Solid State Circuits, vol. 27, pp.1736-1746, Dec. 1992.
    • (1992) IEEE Journal of Solid State Circuits , vol.27 , pp. 1736-1746
    • Lee, T.H.1    Bulzacchelli, J.F.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.