High efficiency 2 GHz power Si-MOSFET design under low supply voltage down to 1V

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1996, Pages 83-86

  Ohguro, T ^a   Saito, M ^a   Morifuji, E ^a   Murakami, K ^a   Matsuzaki, K ^a   Yoshitomi, T ^a   Morimoto, T ^a   Momose, H S ^a   Katsumata, Y ^a   Iwai, H ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EFFICIENCY; POWER MOSFET; ELECTRIC BREAKDOWN; ELECTRIC POWER SUPPLIES TO APPARATUS; GATES (TRANSISTOR); IMPURITIES; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; POWER ELECTRONICS; SEMICONDUCTING SILICON;

DESIGN METHOD; GATE-LENGTH; HIGH POWER; HIGHER EFFICIENCY; LOW SUPPLY VOLTAGES; LOW VOLTAGES; POWER; POWER-ADDED-EFFICIENCY; RF POWER; SI MOSFET;

DESIGN; MOSFET DEVICES;

GATE OXIDE; IMPURITY CONCENTRATION; POWER ADDED EFFICIENCY;

EID: 16744368810     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1996.553127     Document Type: Conference Paper

References (8)

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8. T .Yoshitomi et al., "High performance 0.15pmsingle gate COsalicide CMOS" in Roc of Symp. on VLSI Tech., pp. 34-35, 1996.