Towards synthesis of monotonic asynchronous circuits from signal transition graphs

Proceedings - International Conference on Application of Concurrency to System Design, ACSD

Volumn 2001-January, Issue , 2001, Pages 179-188

  Starodoubtsev, N ^a   Bystrov, S ^a   Goncharov, M ^a   Klotchkov, I ^a   Smirnov, A ^a  

^a INSTITUTE FOR ANALYTICAL INSTRUMENTATION   (Russian Federation)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ASYNCHRONOUS SEQUENTIAL LOGIC; COMPUTER AIDED DESIGN; COMPUTER CIRCUITS; FORMAL LOGIC; LOGIC CIRCUITS; RECONFIGURABLE HARDWARE; SPECIFICATIONS; SYSTEMS ANALYSIS;

ASYNCHRONOUS CIRCUITS; BEHAVIOURAL SPECIFICATIONS; NONMONOTONIC LOGIC; REFINEMENT TECHNIQUES; SIGNAL TRANSITION GRAPHS; SPEED INDEPENDENT; SPEED-INDEPENDENT CIRCUITS; SYNTHESIS METHOD;

LOGIC SYNTHESIS;

EID: 16444379713     PISSN: 15504808     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CSD.2001.981775     Document Type: Conference Paper

References (23)

1. J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno and A. Yakovlev. Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers, IEICE Trans. Inf. and Syst., Vol. E80-D, No.3, March 1997, pp. 315-325.
2. Kees van Berkel. Beware the isochronic fork. Integration, the VLSI jornal, 13(2): 103-128, June, 1992.
3. D. E. Muller and W. S. Bartky. A theory of asynchronous circuits. In Proceedings of an International Symposium on the Theory of Switching, pp. 204-243. Harvard University Press, April 1959.
4. http://www.chips.ibm.com/techlib/products/acics/databooks.html
5. S.B. Furber and J. Liu. Dynamic logic in four-phase micropipelines. Proc. of the Second Int. Symp. on Advanced Research in Asynchronous Circuits and Systems (ASYNC'96) March, 1996 Aizu-Wakamatsu, Japan, pp.11-16.
6. M. Kishinevsky, J. Cortadella, A. Kondratyev and L. Lavagno. Asynchronous interface specification, analysis and synthesis, Proc. DA C'98, pp. 2-7.
7. A. Kondratyev, J. Cortadella, M. Kishinevsky, L. Lavagno, and A. Yakovlev. Logic Decomposition of Speed-Independent Circuits, In Proceedings of the IEEE/, Vol.87, No.2, February 1999, pp. 347-362.
8. G.Mago, "Monotone function in sequential circuits", IEEE Trans. on Computers, Vol. C-22. No. 10, October 1973, pp.928-933.
9. T.Ibaraki, S.Muroga. "Synthesis network with a minimal number of negative gates", IEEE Trans. on Computers, Vol. C-20. No. 1, January 1971
10. C.Piguet. Logic synthesis of race-free asynchronous sequential circuits. IEEE JSSC, vol.26, No 3, March 1991. pp. 371-380.
11. C.Piguet. Synthesis of Asynchronous CMOS Circuits with Negative Gates. Journal of Solid State Devices and Circuits, vol.5, No.2, July 1997.
12. C.Piguet. Design of Speed-Independent CMOS Cells from Signal Transition Graphs. PATMOS'98. Oct.1998, Copenhagen, pp.357-366.
13. N.A.Starodoubtsev. Autonomous Antitone Sequential Circuits. In: Soviet Journal of Computer and System Science(USA),
14. Izvestiya Akademii Nauk SSSR. Technicheskaya Kibernetika (USSR), 1981, No 4 (Part I. Definitions and Interpretetion), No.5 (Part II. Cyclograms and their Properties) and No.6 (Part III. Minimisation).
15. Izvestiya Akademii Nauk SSSR. Technicheskaya Kibernetika (USSR), 1981, No 4 (Part I. Definitions and Interpretetion), No.5 (Part II. Cyclograms and their Properties) and No.6 (Part III. Minimisation).
16. Izvestiya Akademii Nauk SSSR. Technicheskaya Kibernetika (USSR), 1981, No 4 (Part I. Definitions and Interpretetion), No.5 (Part II. Cyclograms and their Properties) and No.6 (Part III. Minimisation).
17. N.A.Starodoubtsev. Asynchronous processes and antitonic control circuits, In: Soviet Journal of Computer and System Science (USA)
18. Izvestiya Akademii Nauk SSSR. Technicheskaya Kibernetika (USSR), 1885, vol.23, No.2, pp.112-119 (Part I. Description Language), No.6, pp.81-87 (Part II. Basic properties), 1986, Vol.24, No.2, pp.44-51 (part III. Realisation).
19. Izvestiya Akademii Nauk SSSR. Technicheskaya Kibernetika (USSR), 1885, vol.23, No.2, pp.112-119 (Part I. Description Language), No.6, pp.81-87 (Part II. Basic properties), 1986, Vol.24, No.2, pp.44-51 (part III. Realisation).
20. Izvestiya Akademii Nauk SSSR. Technicheskaya Kibernetika (USSR), 1885, vol.23, No.2, pp.112-119 (Part I. Description Language), No.6, pp.81-87 (Part II. Basic properties), 1986, Vol.24, No.2, pp.44-51 (part III. Realisation).
21. M.Goncharov, I.Klotchkov, E.Klypkin, A.Smirnov and N.Starodoubtsev. STG refinement for synthesis of negative gates' circuits. Handouts of the AciD-WG Workshop, Univ. of Newcastle upon Tyne, Tech. report No.670, April, 1999.
22. N.Starodoubtsev, M.Goncharov, I.Klotchkov and A.Smirnov. Synthesisof asynchronous interface circuits by STG refinement. Proc. AINT'00 (Asynchronous Interfaces) Delft, the Netherland, July 2000, pp. 65-73.
23. M.Goncharov, I.Klotchkov, A.Smirnov and N.Starodoubtsev. Timing extension of STG model and a method to simulate timed STG behaviour in VHDL environment. Proc of International Conference on Application Concurency to System Design (IC ACSD) 1998, Fukushima, Japan, pp.120-129.