PAD: A new interactive knowledge-based analog design approach

Analog Integrated Circuits and Signal Processing

Volumn 42, Issue 3, 2005, Pages 291-299

  Stefanovic, Danica ^a   Kayal, Maher ^a   Pastre, Marc ^a  

^a EPFL   (Switzerland)

Author keywords

Analog; CAD tools; CMOS circuit design; Knowledge based; Systematic design

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; MATHEMATICAL MODELS; OPERATIONAL AMPLIFIERS; PARAMETER ESTIMATION; PRODUCT DESIGN; TRANSCONDUCTANCE; VISUALIZATION;

ANALOG; CAD TOOLS; CMOS CIRCUIT DESIGNS; SYSTEMATIC DESIGNS;

KNOWLEDGE BASED SYSTEMS;

EID: 16244418136     PISSN: 09251030     EISSN: None     Source Type: Journal    
DOI: 10.1007/s10470-005-6762-9     Document Type: Conference Paper

References (10)

1. C. Enz F. Krummenacher and E.A. Vittoz, "An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications." J. Analog Integrated Circuits and Signal Processing, vol. 8, pp. 83-114, 1995.
2. M. Bucher, C. Lallement, C. Enz, F. Théodoloz, and F. Krummenacher, "The EPFL-EKV MOSFET model equations for simulation, Version 2.6." Technical Report, EPFL, July 1998, available on-line: http://legwww.epfl.ch/EKV
3. D. Binkley, M. Bucher, and D. Foty, "Design-oriented characterization of CMOS over the continuum of inversion level and channel length." The 7th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2000, vol. 1, pp. 161-164, 2000.
4. F. Silveira, D. Flandre, and P.G.A. Jespers, "A gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a Silicon-on-Insulator micropower OTA." IEEE Journal of Solid-State Circuits, vol. 31, no. 9, pp. 1314-1319, 1996.
5. M. Bucher, C. Lallement, and C.C. Enz, "An efficient parameter extraction methodology for the EKV MOST model." In IEEE International Conference on Microelectronic Test Structures Proceedings, ICMTS 1996, 1996, pp. 145-150.
6. R. Spence, "The facilitation of insight for analog design." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 46, no. 5, pp. 540-548, 1999.
7. P. Maulik, L. Carley, and D. Allstot, "Sizing of cell-level analog circuits using constrained optimization techniques." IEEE Journal of Solid-State Circuits, vol. 28, no. 3, pp. 233-241, 1993.
8. D. Stefanovic, M. Kayal, M. Pastre, and V.B. Litovski, "Procedural analog design (PAD) tool." In Fourth International Symposium on Quality Electronic Design Proceedings, ISQED 2003, 2003, pp. 313-318.
9. D. Stefanovic, M. Kayal, and M. Pastre, "PAD: un outil de CAO pour la conception procédurale de cellules intégrées analogiques." 4ème colloque sur le Traitement Analogique de l'Information, du Signal et ses Applications, TAISA'03, Sept. 2003.
10. PAD beta version can be downloaded from: http://legwww.epfl.ch/CSL/