Procedural analog design (PAD) tool

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2003-January, Issue , 2003, Pages 313-318

  Stefanovic, Danica ^a,b   Kayal, Maher ^a   Pastre, Marc ^a   Litovski, Vanco B ^b  

^a EPFL   (Switzerland)

^b UNIVERSITY OF NI   (Serbia)

Author keywords

Analog circuits; Atherosclerosis; Circuit simulation; Circuit topology; Design optimization; Equations; Guidelines; Mirrors; Operational amplifiers; Transconductance

Indexed keywords

AMPLIFIERS (ELECTRONIC); ANALOG INTEGRATED CIRCUITS; CIRCUIT SIMULATION; DESIGN; ELECTRIC NETWORK TOPOLOGY; MIRRORS; OPERATIONAL AMPLIFIERS; TOPOLOGY; TRANSCONDUCTANCE;

ANALOG-DESIGN TOOLS; ATHEROSCLEROSIS; DESIGN OPTIMIZATION; DIFFERENTIAL PAIRS; EQUATIONS; GUIDELINES; PROCEDURAL DESIGNS; TRANSCONDUCTANCE AMPLIFIER;

ANALOG CIRCUITS;

EID: 16244364322     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2003.1194751     Document Type: Conference Paper

References (8)

1. C. Enz F. Krummenacher and E. A. Vittoz, "An Analytical MOS Transistor Model Valid in All Regions of Operation and Dedicated to Low-Voltage and Low-Current Applications", J. Analog Integrated Circuits and Signal Processing, Vol. 8, July 1995, pp. 83-114.
2. M. Bucher, C. Lallement, C. Enz, F. Théodoloz and F. Krummenacher, "The EPFL-EKV MOSFET Model Equations for simulation, Version 2.6" Technical Report, EPFL, July 1998, available on-line: http://legwww.epfl.ch/EKV
3. D.Binkley, M.Bucher, D.Foty, "Design-oriented characterisation of CMOS over the continuum of inversion level and channel length" , The 7th IEEE International Conference on Electronics, Circuits and Systems, 2000. ICECS 2000., Volume: 1 , 2000 , Page(s): 161 -164 vol.1
4. F. Silveira, D. Flandre, P.G.A. Jespers," A gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a Silicon-on-Insulator micropower OTA", IEEE Journal of Solid-State Circuits, 31 (1996) 1314-1319.
5. R. Spence, "The facilitation of insight for analog design", IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Volume: 46 Issue: 5 , May 1999, Page(s): 540 -548
6. P. Maulik, L. Carley, D. Allstot, "Sizing of cell-level analog circuits using constrained optimisation techniques" , IEEE Journal of Solid-State Circuits, Volume: 28 Issue: 3 , March 1993 , Page(s): 233 -241
7. D. Glozić, V. Litovski, and R. Bayford, "ASCOTA3 - A New Automatic Hierarchical CMOS Opamp Synthesizer", Facta Universitatis, series: Electronics and Energetics, Vol. 4, No. 1, 1991, pp. 81-105.
8. D. Glozić, V. Litovski, and R. Bayford, "ASCOTA3 ADIL: A New Reconfigurable CMOS Analogue VLSI Design Framework", Microelectronics Journal, Vol. 25, No. 5, Aug. 1994, pp. 335-351.