메뉴 건너뛰기




Volumn , Issue , 1999, Pages 543-548

Exploring the combination of I/sub DDQ/ and i/sub DDt/ testing: Energy testing

Author keywords

[No Author keywords available]

Indexed keywords

CMOS CIRCUITS; CUSTOM CIRCUITS; DEFECT-FREE; DEFECTIVE CIRCUITS; ENERGY SIGNATURES;

EID: 16244395601     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.1999.761180     Document Type: Conference Paper
Times cited : (4)

References (12)
  • 1
    • 0019029590 scopus 로고
    • Physical versus logic fault models in mos lsi circuits: Impact on their testability
    • June
    • J. Galiay, Y. Crouzet, M. Vergniault, "Physical versus Logic fault Models in MOS LSI Circuits: Impact on their Testability", IEEE Trans, on Computers, June 1980, pp. 527-531.
    • (1980) IEEE Trans, on Computers , pp. 527-531
    • Galiay, J.1    Crouzet, Y.2    Vergniault, M.3
  • 2
    • 0019710943 scopus 로고
    • Cmos is most testable
    • M. Levi, "CMOS is Most Testable", Proc. of ITC, 1981, pp. 217-220.
    • (1981) Proc. of ITC , pp. 217-220
    • Levi, M.1
  • 3
    • 0020290502 scopus 로고
    • A new fault model and testing techniques for cmos devices
    • Y.K.Malaiya, S.Y.H. Su, "A New Fault Model and Testing Techniques for CMOS Devices", Proc. of ITC, 1982, pp. 25-34.
    • (1982) Proc. of ITC , pp. 25-34
    • Malaiya, Y.K.1    Su, S.Y.H.2
  • 5
    • 0026869827 scopus 로고
    • Design and test rules for cmos circuits to facilitate iddq testing of bridging faults
    • May
    • K.J. Lee, M.A. Breuer, "Design and Test Rules for CMOS Circuits to Facilitate Iddq Testing of Bridging Faults", IEEE Trans, on CAD, May 1992, pp. 659670.
    • (1992) IEEE Trans, on CAD , pp. 659670
    • Lee, K.J.1    Breuer, M.A.2
  • 6
    • 3242831535 scopus 로고    scopus 로고
    • Test of cmos circuits based on their energy consumption
    • October
    • M.A. Ortega, J. Rius, J. Figueras, "Test of CMOS Circuits based on their Energy Consumption", IDDQ'96, October 1996, pp. 36-40.
    • (1996) IDDQ'96 , pp. 36-40
    • Ortega, M.A.1    Rius, J.2    Figueras, J.3
  • 9
    • 0023533795 scopus 로고
    • A new approach to dynamic idd testing
    • M. Keating, D. Meyer, "A New Approach to Dynamic IDD Testing", Proc. of ITC'87, pp. 316-319, 1987.
    • (1987) Proc. of ITC'87 , pp. 316-319
    • Keating, M.1    Meyer, D.2
  • 10
    • 0032320511 scopus 로고    scopus 로고
    • Process-tolerant test with the energy consumption ratio
    • October
    • B. Vinnakota, W. Jiang, D. Sun, " Process-Tolerant Test with the Energy Consumption Ratio", Proc. of ITC'98, pp. 1027-1036, October 1998.
    • (1998) Proc. of ITC'98 , pp. 1027-1036
    • Vinnakota, B.1    Jiang, W.2    Sun, D.3
  • 11
    • 0029251036 scopus 로고
    • Transient power supply current monitoring-a new test method for cmos vlsi circuits
    • February
    • S.T. Su, R.Z. Makki, T. Nagle, "Transient Power Supply Current Monitoring-A New Test Method for CMOS VLSI Circuits", JETTA, 6:23-43, February, 1995.
    • (1995) JETTA , vol.6 , pp. 23-43
    • Su, S.T.1    Makki, R.Z.2    Nagle, T.3
  • 12
    • 84893605269 scopus 로고
    • An approach to dynamic power consumption current testing of cmos ics
    • April
    • J. A. Segura, M. Roca, D. Mateo, A. Rubio, "An Approach to Dynamic Power Consumption Current Testing of CMOS ICs", . Proceedings of VTS'95, pp. 95100, April 1995.
    • (1995) . Proceedings of VTS'95 , pp. 95100
    • Segura, J.A.1    Roca, M.2    Mateo, D.3    Rubio, A.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.