Efficient LUT-based FPGA technology mapping for power minimization

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2003-January, Issue , 2003, Pages 353-358

  Li, Hao ^a   Mak, Wai Kei ^a   Katkoori, S ^a  

^a University of South Florida   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; ELECTRIC POWER UTILIZATION; MAPPING; RECONFIGURABLE HARDWARE;

FPGA TECHNOLOGY; INCREMENTAL NETWORKS; LOW POWER; MAPPING SELECTION; NP-HARD; POWER MINIMIZATION; TECHNOLOGY MAPPING;

LOW POWER ELECTRONICS;

EID: 16244364506     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2003.1195040     Document Type: Conference Paper

References (20)

1. R. K. Ahuja, T. L. Magnanti, and J. B. Orlin, Network Flows - Theory, Algorithms, And Applications, Prentice Hall, 1993.
2. C. Bhat, and N. N. Chiplunkar, "Routability-driven technology mapping for lookup table-based FPGAs", in 12th International Conference on VLSI Design, pp. 390-393, Jan. 1999.
3. S. D. Brown, R. J. Francis, J. Rose, and Z. G. Vranesic, Field Programmable Gate Arrays, Kluwer Academic Publishers, 1995.
4. K.-C. Chen, J. Cong, Y. Ding, A. Kahng, and P. Trajmar, "DAG-Map: graph-based FPGA technology mapping for delay optimization", IEEE Design and Test of Computers, pp. 7-20, 1992.
5. J. Cong, and Y. Ding, "An optimal technology mapping algorithm for delay optimization in look-up table based FPGA designs", in International Conference on Computer Aided Design, pp. 213-218, Nov. 1992.
6. A. H. Farrahi, and M. Sarrafzadeh, "Complexity of the lookup-table minimization problem for FPGA technology mapping", in IEEE Transactions on Computer-Aided Design, vol. 13(11), pp 1319-1332, Nov. 1994.
7. A. H. Farrahi, and M. Sarrafzadeh, "FPGA technology mapping for power minimization", in 4th International Workshop on Field Programmable Logic and Applications, pp. 66-77, September 1994.
8. R. J. Francis, J. Rose, and K. Chung, "Chortle: A technology mapping for lookup table-based field programmable gate arrays", in 27th ACM/IEEE Design Automation Conference, pp. 613-619, June 1990.
9. R. J. Francis, J. Rose, and Z. Vranesic, "Chortle-crf: fast technology mapping for lookup table-based FPGAs", in 28th ACM/IEEE Design Automation Conference, pp. 227-233, June 1991.
10. K. Karplus, "Xmap: A technology mapper table-lookup field-Programmable gate arrays", in 28th ACM/IEEE Design Automation Conference, pp. 240-243, June 1991.
11. Y.-T. Lai, M. Pedram, and S. Sastry, "BDD based decomposition of logic functions with application to FPGA synthesis", in 30th ACM/IEEE Design Automation Conference, pp. 230-235, June 1993.
12. R. Murgai, N. Shenoy, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Improved logic synthesis algorithms for table look up architectures", in International Conference on Computer Aided Design, pp. 564-567, Nov. 1991.
13. F. Najm, "Transition Density: A new measure of activity in digital circuits", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 310-323, Feb. 1993.
14. P. Sawkar, and D. E. Thomas, "Technology for table-look-up based field programmable gate arrays", in ACM/SIGDA Workshop on Field Programmable Gate Arrays, pp. 83-88, Feb. 1992.
15. M. Schlag, J. Kong, and P. K. Chan, "Routability-driven technology mapping for lookup table-based FPGAs", in IEEE International Conference on Computer Design, pp. 86-90, October 1992.
16. N. Togawa, M. Sato, and T. Ohtsuki, "Maple: A simultaneous technology mapping, placement and global routing algorithm for field-programmable gate arrays", in International Conference on Computer Aided Design, pp. 155-163, 1994.
17. Z.-H. Wang, E.-C. Liu, J. Lai, and T.-C. Wang, "Power minimization in LUT-based FPGA technology mapping", in ASP-DAC, pp. 635-640, 2001.
18. N. Weste, and K. Eshraghian, Principles of CMOS VLSI Design: A System Perspective, Addison-Wesley Reading, 1993.
19. J. Cong, and Y. Ding, "On area/depth trade-off in LUT-based FPGA technology mapping", IEEE Trans. on VLSI Systems, vol. 2, no. 2, pp. 137-148, June 1994.
20. J. Cong, and Y.Y. Hwang, "Simultaneous depth and area minimization in LUT-based FPGA mapping", in Proc. Int. Symp. on Field Programmable Gate Arrays, pp. 68-74, 1995.