Heuristic technology mapper for LUT based FPGAs

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 1999, Pages 390-393

  Bhat, Chitrasena ^a   Chiplunkar, Niranjan N ^a  

^a SRI JAYACHAMARAJENDRA COLLEGE OF ENGINEERING   (India)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; HEURISTIC METHODS; LOGIC DESIGN; OPTIMIZATION; TABLE LOOKUP;

HEURISTIC TECHNOLOGY MAPPERS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0032715193     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/icvd.1999.745187     Document Type: Conference Paper

References (13)