Modeling of power distribution networks with retardation using the transmission matrix method

IEEE Topical Meeting on Electrical Performance of Electronic Packaging

Volumn , Issue , 2004, Pages 233-236

  Watanabe, Takayuki ^a   Srinivasan, Krishna ^b   Asai, Hideki ^c   Swaminathan, Madhavan ^b  

^a UNIVERSITY OF SHIZUOKA   (Japan)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^c SHIZUOKA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; ELECTRIC RESISTANCE; INDUCTANCE; RESONANCE; SIGNAL THEORY; SWITCHING SYSTEMS;

DECOUPLING CAPACITORS; EQUIVALENT SERIES RESISTANCE (ESR); POWER DELIVERY SYSTEMS; TRANSMISSION MATRIX METHOD (TMM);

ELECTRIC POWER DISTRIBUTION;

EID: 15944378212     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. L. Polka, S. Chickamenahalli, C.Y. Chung, D.G. Figucroa, V.L. Li, K. Merley, D. Wood and L. Zu, "Package-Level Interconnect Design for Optimum Electrical Performance," Intel Technology Journal Q3, 2000.
2. N. Na, J. Choi, S. Chun, M. Swaminathan, and J. Srinivasan, "Modeling and transient simulation of planes in electromagnetic packages," IEEE Trans. Comp., Packag., Manufact. technol. B, vol. 21, pp. 157-163, May. 1998.
3. L. Smith, R. Raymond, and T. Roy, "Power plane spice models and simulated performance for materials and geometries, " IEEE Trans. Adv. Packag. vol. 24, pp. 277-287, Aug. 2001.
4. J.H. Kim, and M. Swaminathan, "Modeling of Multilayered Power Distribution Planes Using Transmission Matrix Method," IEEE Trans. Adv. Packag. vol. 25, pp. 189-199, May. 2002.
5. K.S. Oh, J.E. Schutt-Aine, R. Mittra, and B. Wang, "Computation of the equivalent capacitance of a via in a multilayered board using the closed-form Greens fonction," IEEE Trans. Microwave Theory Tech, vol. 44, pp. 347-349, Feb. 1996.
6. P. J. Restle, A.E. Ruehli, S.G. Walker, and G. Papadopoulos, "Full-Wave PEEC Time-Domain Method for the Modeling of On-Chip Interconnects," IEEE Trans. Computer-Aided Design, vol.20, pp.877-887, July 2001.
7. R. Achar, M.S. Nakhla, "Simulation of high-speed interconnects, " Proceedings of the IEEE, vol. 89, No. 5, pp.693-728, May 2001.
8. M. Kamon, M.J. Tsuk, and J. White, "Fasthenry: A multipole-accclerated 3-d inductance extraction program," IEEE Transactions on Microwave Theory and Techniques, vol. 42, pp. 1750-1758, Sept. 1994.