Modeling and mitigating AC common mode conversion in multi-Gb/s differential printed circuit boards

IEEE Topical Meeting on Electrical Performance of Electronic Packaging

Volumn , Issue , 2004, Pages 29-32

  Heck, Howard ^a   Hall, Stephen ^a   Horine, Bryce ^a   Liang, Tao ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INSERTION LOSS; MODE CONVERSION; SIGNAL AMPLITUDE; TIMING MARGINS;

COMPUTER SIMULATION; ELECTRIC POTENTIAL; FREQUENCIES; PARAMETER ESTIMATION; PERMITTIVITY; SIGNAL PROCESSING; TIME DOMAIN ANALYSIS;

PRINTED CIRCUIT BOARDS;

EID: 15944371550     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. H. Heck, et. al., 'Impact of FR4 Dielectric Non-uniformity on the Performance of Multi-Gb/s Differential Signals," IEEE Electrical Performance of Electronic Packaging, October 2003, pp. 243-246.
2. B.K. Casper, et. al., "An Accurate and Efficient Analysis Method for Multi-Gb/s Chip-to-Chip Signaling Schemes," 2002 Symposium on VLSI Circuits Digest of Technical Papers, June 2002, pp. 54-57.
3. W. Dally, J. Poulton, "Transmitter Equalization for 4-Gbps Signaling," IEEE Micro, January/February 1997, pp. 48-46.
4. G. Brist, et. al., "High Speed Interconnects: The Impact of Spatial Electrical Properties of PCB due to Woven Glass Reinforcement Patterns," IPC Printed Circuits Expo, February 2004.