Optimizing Power While Exploiting Fine Grain Parallelism on FPGAs

Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems

Volumn 15, Issue 1, 2003, Pages 357-362

  Jiang, Tianyi ^a   Tang, Xiaoyong ^a   Jones, Alex ^a   Banerjee, Prith ^a  

^a Northwestern University   (United States)

Author keywords

FPGA; IP core; PACT HDL compiler; Power optimization

Indexed keywords

ALGORITHMS; C (PROGRAMMING LANGUAGE); CMOS INTEGRATED CIRCUITS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; ELECTRIC POWER SUPPLIES TO APPARATUS; FIELD PROGRAMMABLE GATE ARRAYS; FIR FILTERS; LARGE SCALE SYSTEMS; MATHEMATICAL OPERATORS; MATRIX ALGEBRA; MICROPROCESSOR CHIPS; PROGRAM COMPILERS; SIGNAL PROCESSING;

IP CORE; PACT HDL COMPILERS; POWER OPTIMIZATION;

PARALLEL PROCESSING SYSTEMS;

EID: 1542432996     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (20)

1. J. Rabaey and M. Pedram, Low Power Design Methodologies (Kluwer Academic Publishers, 1996).
2. A. Raghunathan, N. K. Jha, and S. Dey, High-level Power Analysis and Optimization (Kluwer Acad. Publisher, 1998).
3. F. Gruian and K. Kuchcinski, Operation Binding and Scheduling for Low Power Using Constraint Logic Programming, Proceedings of EuroMICRO, 1998.
4. D. Singh, J. Rabaey, M. Pedram, F. Catthoor, S. Rajgopal, N. Sehgal, T. Mozdzen, Power Conscious CAD Tools and Methodologies: A Perspective, Proceedings of the IEEE, Vol. 83, No. 4, April 1995.
5. De Micheli, G. Ku D. Mailhot, F. Truong T, The Olympus Synthesis System for Digital Design, IEEE Design & Test of Computer, 1990.
6. Esterel-C Language (ECL), www.cadence.com.
7. CynApps Suite, Cynthesis Applications for Higher Level Design, www.cynapps.com.
8. Overview of the Open SystemC Initiative, SystemC website, www.systemc.org.
9. Adelante Technologies, A|RT Builder. www.adelantetechnologics.com.
10. Celoxica Inc., Handle C compiler, www.celoxica.com.
11. M. Haldar, A. Nayak, A. Choudhary, and P. Banerjee, A System for Synthesizing Optimized FPGA Hardware from MATLAB, Proc. ICCAD, San Jose, CA, November 2001.
12. A. P. Chandrakasan, S. Sheng, R. W. Brodersen, Low Power CMOS Digital Design, IEEE Journal of Solid-State Circuit, 1992.
13. A. P. Chandrakasan, M. Potkonjak, R. Mehra, J. Rabaey, R. W. Brodersen, Optimizing Power Using Transformations, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 1995.
14. E. Musoll, J. Cortadella, High-level Techniques for Reducing the Activity of Functional Units, Proceedings of the International Symposium on Low Power Design, 1995.
15. G. Lakshminarayana, A. Raghunathan, K. S. Khouri, N. K. Jha, S. Dey, Common-Case Computation: A High-Level Technique for Power and Performance Optimization, Proc. of the Design Automation Conference (DAC), 1999.
16. R. P. Wilson, R. S. French, C. S. Wilson, S. P. Amarasinghe, J. M. Anderson, S. W. K. Tjiang, S. W. Liao, C. W. Tseng, M. W. Hall, M. S. Lam, J. L. Hennessy, SUIF: An Infrastructure for Research on Parallelizing and Optimizing Compilers. SIGPLAN Notices, 1994.
17. Synplify, Synplicity, www.synplicity.com.
18. Synopsys, Design Compiler, FPGA Compiler and DesignWare IP, www.synopsys.com.
19. Xilinx, Virtex Datasheet, www.xilinx.com.
20. Model Technology, ModelSim, HDL Simulator, www.model.com.