Partial element equivalent circuit (PEEC) models for on-chip passives and interconnects

International Journal of Numerical Modelling: Electronic Networks, Devices and Fields

Volumn 17, Issue 1, 2004, Pages 61-84

  Verbeek, Menno E ^a  

^a EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

EFIE; Electromagnetism; Equivalent circuit; Integral equation; PEEC; Retardation

Indexed keywords

COMPUTER SIMULATION; ELECTRIC CLOCKS; ELECTRIC INDUCTORS; ELECTROMAGNETISM; EQUIVALENT CIRCUITS; FINITE DIFFERENCE METHOD; FINITE ELEMENT METHOD; GALERKIN METHODS; INTEGRAL EQUATIONS; MAXWELL EQUATIONS; TIME DOMAIN ANALYSIS;

ELECTRIC FIELD INTEGRAL EQUATIONS (EFIE); PARTIAL ELEMENT EQUIVALENT CIRCUITS (PEEC); RETARDATION;

MICROPROCESSOR CHIPS;

EID: 1542364461     PISSN: 08943370     EISSN: None     Source Type: Journal    
DOI: 10.1002/jnm.524     Document Type: Article

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