Analysis of FSRAM Single Bit Failures Due to Unique Dislocations

Conference Proceedings from the International Symposium for Testing and Failure Analysis

Volumn , Issue , 1998, Pages 373-376

  Schani, P ^a   Subramanian, S ^a   Soorholtz, V ^a   Liston, P ^a   Moss, J ^a   Widener, E ^a   Chu, A ^a  

^a MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

JUNCTION LEAKAGE; LIGHTLY DOPED DRAIN (LDD) PROCESS;

DATA STORAGE EQUIPMENT; ETCHING; FAILURE ANALYSIS; HYDROFLUORIC ACID; INTEGRATED CIRCUITS; RESISTORS; SCANNING ELECTRON MICROSCOPY; SEMICONDUCTOR JUNCTIONS; STRESSES; TRANSMISSION ELECTRON MICROSCOPY;

RANDOM ACCESS STORAGE;

EID: 1542330904     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. S. Subramanian, P Schani, Ed Widener, Pat Liston, Jamey Moss, Vince Soorholtz, A Selected Area Planar TEM (SAPTEM) Sample Preparation Procedure for Failure Analysis of Intergrated Circuits.Proceedings from the 24th International Symposium for Testing and Failure Analysis, (1998)
2. R.B. Marcus and T.T. Sheng, Transmission Electron Microscopy of Silicon VLSI Circuits and Structures. John Wiley & Sons, New York, (1983)