Failure Analysis Process Flow and Common Failure Mechanisms in Flip-chip Packaged Devices

Conference Proceedings from the International Symposium for Testing and Failure Analysis

Volumn , Issue , 2000, Pages 107-115

  Hsiung, Steve ^a   Chan, Victer ^a  

^a AGERE SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTERCONNECT TECHNOLOGY; TIME DOMAIN REFLECTOMETRY (TDR);

ACOUSTIC EMISSION TESTING; CHIP SCALE PACKAGES; DIES; EMISSION SPECTROSCOPY; ENERGY DISPERSIVE SPECTROSCOPY; FAILURE ANALYSIS; INSPECTION; OPTICAL TESTING; PROCESS CONTROL; REFLECTOMETERS; SOLDERING; SPECTRUM ANALYSIS; TIME DOMAIN ANALYSIS;

FLIP CHIP DEVICES;

EID: 1542270849     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. LSI Logic Flip-chip Ball Grid Array (FC-BGA) Package Technology Datasheet, October 1997.
2. Charles Odegard, Craig Lambert, Comparative TDR Analysis as a Packaging FA Tool, ISTFA proceeding (1999), 49-55.
3. John H. Lau, Flip Chip Technologies, MCGraw-Hill.
4. David L. Burgess, O.D. Trapp, Failure & Yield Analysis Handbook.
5. Lawrence C. Wagner, etc., Failure Analysis of Integrated Circuits, Tools and Techniques, Kluwer Academic Publishers.