Use of STEM in Nanometer Level Defect Analysis of SRAM Devices

Conference Proceedings from the International Symposium for Testing and Failure Analysis

Volumn , Issue , 2001, Pages 313-317

  Wang, Nathan ^a   Daniel, Sabbas ^a   Becker, Daniel ^b   Mcilwrath, Kevin ^b  

^a CYPRESS SEMICONDUCTOR   (United States)

^b Hitachi Scientific Instruments   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TEST EQUIPMENT (ATE); DEFECT ANALYSIS; SCANNING TRANSMISSION ELECTRON MICROSCOPY (STEM);

CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; ETCHING; FAILURE ANALYSIS; FIELD EMISSION MICROSCOPES; IMAGE ANALYSIS; SCANNING ELECTRON MICROSCOPY; STATIC RANDOM ACCESS STORAGE; TRANSISTORS; TRANSMISSION ELECTRON MICROSCOPY;

DATA STORAGE EQUIPMENT;

EID: 1542270695     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. David P. Vallett, Failure Analysis of Integrated Circuits, Kluwer Academic Publishers, 1999, P.246.
2. R.J.Keyse et al, "Introduction to Scanning Transmission Electron Microscopy", 1st Edn, Springer-Verlag, New York, 1998, P.51
3. th International Symposium for Testing and Failure Analysis, ASM International, 1999, P.352.
4. P. B. Hirsch et al, Electron Microscopy of Thin Crystals, Butterworths, 1965, P.3.
5. James Buchanan, CMOS/TTL Digital Systems Design, McGrow-Hill Publishing Co., 1990, P.48.