A power-aware SWDR cell for reducing cache write power

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn 2003-January, Issue , 2003, Pages 14-17

  Chang, Yen Jen ^a   Yang, Chia Lin ^a   Lai, Feipei ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Bridge circuits; Circuit stability; Data mining; Energy consumption; Microprocessors; Permission; Random access memory; Tail; Voltage; Writing

Indexed keywords

BRIDGE CIRCUITS; CELLS; CYTOLOGY; DATA MINING; ELECTRIC POTENTIAL; ENERGY UTILIZATION; HAND HELD COMPUTERS; MICROPROCESSOR CHIPS; POWER ELECTRONICS; POWER MANAGEMENT; RANDOM ACCESS STORAGE; STATIC RANDOM ACCESS STORAGE; TECHNICAL WRITING;

CACHE POWER CONSUMPTION; CIRCUIT STABILITY; CRITICAL COMPONENT; HIGH PERFORMANCE PROCESSORS; LOW POWER TECHNIQUES; PERMISSION; RANDOM ACCESS MEMORY; TAIL;

LOW POWER ELECTRONICS;

EID: 1542269611     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LPE.2003.1231826     Document Type: Conference Paper

References (5)

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