An embedded DRAM for MDLNS FIR filter

Conference Proceedings - 2nd Annual IEEE Northeast Workshop on Circuits and Systems, NEWCAS 2004

Volumn , Issue , 2004, Pages 177-180

  Zhang, Wenjing ^a   Jullien, Graham ^a  

^a UNIVERSITY OF CALGARY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; ELECTRIC POTENTIAL; FIR FILTERS; LOGIC DESIGN; TRANSISTORS;

BITLINE CAPACITANCE (CBL); INNER PRODUCT STEP PROCESSOR (IPSP); LOOK UP TABLE (LUT); WORDLINE (WL);

DYNAMIC RANDOM ACCESS STORAGE;

EID: 14844333290     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. V.S Dimitrov, G.A. Jullien and W.C. Miller. "Theory and Applications of the Double Base Number System." IEEE Trans. on Computers, pp. 1098-1106, vol 48. Oct. 1999.
2. G.A Jullien, V.S. Dimitrov, B. Li, W.C Miller, A. Lee, and M. Ahmadi. "A Hybrid DBNS Processor for DSP Computation." Proc. IEEE International Symposium on Circuits and Sytems, pp.15-18, Orlando, FL, USA, 1999.
3. W. Zhang, J. Eskritt, G.A. Jullien and V.S. Dimitrov. "A 2-D LNS FIR Filter with a Programmable Second Base Using DRAMs", Proc. ESTImedia 1st Workshop on Embedded Systems for Real-Time Multimedia, pp.124-127, Newport Beach, CA, USA, 2003.
4. Barth, J.E.J., et. al., "Embedded DRAM design and architecture for the IBM 0.11-um ASIC offering", IBM Journal of Research and Development, pp. 675-89, v. 46 no. 6 (November 2002).
5. J. Poulton, "An embedded DRAM for CMOS ASICs,", Proc. 17th Conf. on Advanced Research in VLSI, pp. 288-302, IEEE CS, Sept. 1997.
6. Brent Keeth, R. Jacob Baker, "Dram Circuit Design : A Tutorial", IEEE, 2001
7. Jan Rabaey, "Digital Integrated Circuits: A Design Perspective", Prentice Hall, 1996
8. R.F.Hobson., "High-Speed, Low Power Embedded Dynamic Random Access Memory", Proc. Canadian VLSI Conference, pp. 5a1-5a8, Banff, 1993